1. Low-Power Design Techniques for Embedded Systems
Speaker : Kuei-Chung Chang （張貴忠）
National Chung Cheng University
Computer Science and Information Engineering Department
Low-Power Design Techniques for Embedded Systems
晶片系統設計實驗室

2. Outline
Introduction
Low-power designs for embedded systems
The proposed low-power designs - NOC
Future interesting trends
Summary

3. Low-Power Designs for Embedded Systems The proposed Low-Power designs
Outline
Introduction
What is embedded system?
Why Low-Power Designs?
Examples in our life.
Low-Power Designs for Embedded Systems
The proposed Low-Power designs
Future interesting trends
Summary

4. What is Embedded System?
An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions.
Designers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance.
Today
[ Source：Michael Barr, Embedded Systems Glossary, Netrino Technical Library. ]

5. Why we need Low-Power designs?
Mobile devices / Embedded Systems / SOC
Mobile embedded systems that operate with a limited energy source such as batteries.
How to extend the execution time?
Battery technology [X]
Optimizations for embedded systems
Lower the cooling costs of embedded systems.
Main reason …

6. [ Source：http://www.asus.com.tw ]
Example of low-power system
Nookbook’s power management system
[ Source： ]

7. But, …… How about non-mobile devices. (Question from Prof
But, …… How about non-mobile devices? (Question from Prof. Hsueh in CCU)

8. Examples in our life 變頻冷氣
傳統的「定頻式」冷氣壓縮機轉速固定不變，當室溫過冷或過熱時，壓縮機就自行停止或是開啟運轉，冷房溫度忽冷忽熱，壓縮機更因啟動頻繁較為耗電。
由先進控制模組按室內溫度高低變化，自動計算出最適當的驅動頻率，不會陡然啟動或停止壓縮機，達成最佳省電效果。
[ Source： ]

9. Examples in our life 多門省電變頻冰箱
卡通「我們這一家」的花媽說：
開門角度不超過15度，時間不超過一秒最省電
怎麼拿東西呢？
Step 1 ： Space plan
Step 2 ： Snapshot
Step 3 ： Quick hand ……
[ Source： ]

10. Examples in our life 油、電混和車
車內搭載汽油引擎和電力馬達兩種驅動系統
引擎發動時，可以將汽油燃燒時未完全轉換成動能的熱力，轉化為電力，儲貯在電池內
當汽車慢速行駛時，會自動切到電動系統，用電池內儲貯的電力驅動馬達行駛，所以比一般汽車節省四成的燃油。
[ Source： ]

11. So, low-power designs are in anywhere！

12. Low-Power Designs for Embedded Systems
Outline
Introduction
Low-Power Designs for Embedded Systems
Categories of system-level power management techniques
Design levels for embedded systems
Application, Compiler, OS, Architecture, HW
Estimation of power consumption
The proposed Low-Power designs
Future interesting trends
Summary

13. What is power consumption?
PTotal := PDynamic + PStatic , E := V2 x Ncycle
Dynamic power (PDynamic = αCV2fclk/2)
The dynamic component is the switching power, which is the power the device loses when the circuit capacitances charge and discharge.
Static power (leakage power)
The circuit consumes static or leakage power while the clocks are stopped.
Example：
Our body …

14. Categories of system-level power management techniques – 1.DVS
Dynamic Voltage Scaling (DVS / DFS)
One of the most effective design techniques in minimizing the energy consumption (PDynamic = αCV2fclk/2)
When the application does not require peak performance, the clock speed (and its corresponding V) can be dynamically adjusted to the lowest level
Example：T1’s deadline is 25ms, on 50MHz clock + 5V
deadline
deadline
V=5
84% energy reduction T1
V=2 T1 T T
10ms
25ms
10ms
25ms

15. Categories of system-level power management techniques – 1.DVS
Two kinds of DVS scheduling
Intra-task DVS
Adjust the voltage within an individual task boundary
The main feature is how to select the program locations where the voltage and clock will be scaled.
Inter-task DVS
Determine the voltage on a task-by-task basis at each scheduling point
Slack estimation and distribution V T1 V T1 T1 T3 T1 T2 T T

16. Categories of system-level power management techniques – 2.DPM
Dynamic Power Management (DPM)
Place idle components into lower power states selectively.
[ Source：Comparing System-Level Power Management Policies, Yung-Hsiang Lu, IEEE Design & Test of Computers, 2001 ]

17. Categories of system-level power management techniques – 2.DPM
Break event time
Idle for long enough to recuperate the cost of transitioning in and out of the state. [ Shutdown time(sd) + Wakeup time(wu) ]
Need to predict the idle period precisely
Timeout based
Predictive
Stochastic [event-driven approach]
[ Source：Comparing System-Level Power Management Policies, Yung-Hsiang Lu, IEEE Design & Test of Computers, 2001 ]

18. Power-aware technology at all levels
Power reduction can occur at each design stage.
The greatest benefit comes at the system level.
The least benefit is at the circuit level.
design time
power gain
Run-Time/O.S.
Instruction Set
Source Code
Compiler
Algorithm
Microarchitecture
Circuit Design
Application
Fabrication Technology 5%
15%
30%
75%
J. Sproch. “High Level Power Analysis and Optimization. Tutorial,” International Symposium on Low Power Electronics and Design.

19. Power-aware technology at all levels - CAD Tools
Behavioral synthesis using voltage scheduling
Logic level synthesis using gate sizing
Power gating

20. Power-aware technology at all levels - Architecture
Partitioning
Hierarchies
Information encoding
Clock gating (pipeline)
Behavior
high-level
components
behavioral
system model
composition
operators
Architecture
mapping
parameterizable
components
system
architecture
busses, protocols

21. Power-aware technology at all levels - Compiler
High-level loop and data transformations
Transform loops and select data layout to minimize power consumed in data transfers among caches
Low-level compiler optimizations
Operation scheduling, redundant operation elimination, information encoding, code compaction
Bit-width analysis
In applications needing phases of narrow width-operands, use functional units with precisely the bit widths required, shut down other parts
Register allocation:
Assignment of physical registers so as to guarantee a low number of memory spills

22. Design flow for compiler phase
Intermediate Representation C P
Cues
Program
Extract
Parallelism;
High-level
Optimizations
MODELS
Mathematical
Physics-based
...
Instruction Scheduling
Register Allocation
Caches
Hardware Descriptions
ARM/StrongARM
Gated Clocks
Variable Frequency Clocks
Substrate Back-Bias
Dual Voltage Supply
Code Generation
Validation
Execution Platform
Power * Performance Feedback

23. Power-aware technology at all levels - Real-time Operation System
DPM OS
Control system
resources. It can also
control the power states
of the resources
Power Consumption
Power
Saving
ACPI - Power Saving Modes
Work
Sleep
Deep
Off
Need to develop
power management
policies
ACPI
(Advanced Configuration and
Power Interface)
provides an interface
between the OS and
system resources
Application Program Interface
Kernel
Device Drivers
Program 1
Program 2
Program 3
CPU
Monitor
Hard Disk
System Resources

24. Power-aware technology at all levels - Real-time Operation System
[ Source：Power Aware Software Architecture. Rajesh K. Gupta. University of California, Irvine. ]

25. Power-aware technology at all levels
Power-aware technology at all levels - Application Algorithm , Protocols
Choose best algorithm from power characterized functions or protocols.
Example： 「Application-driven Power Management for Mobile Communication」, ACM Wireless Networks (WINET), 2000
Suspending the wireless Ethernet card during idle periods in comm.
Mobile host acts as a master
Tell the slave when data transmission can occur.
Base station acts as a slave
Only allowed to send data to the master during specific phases of the protocol.
During non-transmit phases, it queues up data and waits for commands from the master.
Power savings of up to 83% for communication

27. Power Aware Technology At All Levels - Cross-layer collaboration
Issues
PMH (Power Management Hint)
Inserted by compiler
PMP (Power Management Point)
Start to check by OS
[ Source：N. AbouGhazaleh, Energy management for real-time embedded applications with compiler support, in Proc. of Conference on Language, Compiler, and Tool Support for Embedded Systems, 2002 ]

28. Power Consumption Estimation and monitoring Methodologies
Measurement-based estimation
Quite accurate
Not easy to obtain correct measurements because of higher frequencies.
Embedded systems programmers lack the skills to properly operate it
Simulation-based energy estimation
Power-analysis tool can accurately estimate the energy consumption in the lower abstraction levels, such as the switch or gate levels.
It’s too expensive, slow, and indirect to use for embedded software development
Nanosim, etc.

29. So, … Two-Phase System-Level Design Flow
Phase I. Off-line power measurement
Phase II. On-line power estimation
Simulator
Power
Models
Netlist file
Assembly
Code
Performance
and
Power
Statistics
Compiler
How the information in the energy database was obtained ?
C - Program

30. Method I：Measurement
Consisted of pairs of instructions repeated numerous times within a loop body

31. Method II：Power simulation tool
ModelSim VHDL simulator / NanoSim
It measures the energy variation of the CPU core by changing the instruction-level energy-sensitive factors at each pipeline stage
Opcodes、Instruction fetch address、Register numbers、Register values、Data fetch addresses、immediate operand values

32. [ source ：V. Tiwari, S. Malik and A
[ source ：V. Tiwari, S. Malik and A. Wolfe, “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization, ” IEEE Trans. on Very Large Scale Integration Systems, vol. 2, pp , Dec ]

33. Then, we can do system-level designs…
Then, we can do system-level designs… Example : Energy analysis framework
[Source : V. Tiwari, T.C. Lee, M. Fujita, and D. Maheshwari. Power analysis of the SPARClite MB Technical Report FLA-CAD-94-01, Fujitsu Labs of America ]

34. Low-Power Designs for Embedded Systems
Outline
Introduction
Low-Power Designs for Embedded Systems
The proposed Low-Power designs - NOC
Low-power interconnect architecture Architecture-level optimization ( To appear in ACM Transactions on Design Automation of Electronic Systems, 2007 )
Future interesting trends
Summary

35. Motivation
Designers can integrate dozens of preexisting components such as processors, DSPs, memory arrays, which we call cores.
On-chip networks (NoCs) have becoming the main communication architecture, replacing dedicated interconnections and shared buses.
As the number of cores on a chip increases, power consumed by the communication structure takes significant portion of the overall power-budget. (20%~36%)

36. Optimization I :
Low-Power Topology Construction
Optimization II :
Partially Dedicated Path by Predeterminging Switching Mode

37. Optimization I : - Low-Power Topology Construction
How to allocate? 1 2 3
Low Power 4 7 6 5
Cores
Interconnection architectures

38. Key idea
The energy consumption of sending one bit of data is
To allocate high communicative cores in CCBs or near CCBs to minimize the communication cost by profiling the characteristics of applications.
Localization
Shorter paths
Lower power
Higher performance

39. Design steps Profiling applications Get communication characteristics
Core Flow Graph (CFG)
Allocate cores into irregular topologies
Switch Topology Tree (STT)
Cost model
Communication distance of each message (CDist)
Total communication cost (Cost)

40. 10 4 1 2 3 2
CFG 7 2 5 4 8 3 7 6 5 2 1

41. STT：Backbone

42. How to cluster? 10 4 1 2 3 2 7 2 5 4 8 3 7 6 5 2 1 1 CFG：Application 2
High communicative cores clustered into a block for short com. paths 10 4 1 2 3 2
How to cluster?
Need a cost model 7 2 5 4 8 3 7 6 5 2 1 1
CFG：Application 2 6
STT：Architecture

43. Total communication cost

44. Example 1 2 3 4 5 6 7 10 8 Power-aware Placement 6 7 3 2 5 1 4 3 4 7 2
[ ] x ESbit +
[2] x (2ESbit+ELbit) +
[4+8+1] x + (3ESbit+2ELbit) = 72ESbit + 28ELbit 6 7 3 2 5 S1 S2 S3 1 2 3 4 5 6 7 10 8 1 4 3 4 7 2 5 S1 S2 S3
[ ] x ESbit +
[2+3] x (2ESbit+ELbit) +
[ ] x + (3ESbit+2ELbit) = 93ESbit + 49ELbit 1 6
Other Placement

45. Construction Algorithm： Step 1：construct the backbone10 15 12 1 2
= 27
Basic idea 1 2 6 7 5 15 17
= 32 1 6 2 6
Gomory-Hu cut tree 10 4 1 2 3 2 7 4 7 2 5 4 2 8 5 1 2 6 3 5 3 7 6 5 2 1 15 16 13 5

46. Cluster 3 adjacent cores
Min-cut 7 4 C1 C2 2 5 1 2 6 3 5 15 16 13 5

47. Construction Algorithm： Step 2：Optimization
Special case
When the weight of edges are too close and more than two clusters can be combined.
After Clustering
Cluster shifting

48. Construction Algorithm： Step 3：Physical switch mapping
Assign a crossroad switch to a cluster
Recursively cluster 3 max-weight clusters into a supercluster and assign a crossroad switch (min-cut of clusters) S1 1 6 2 4 5 S3 3 S2 7

49. Multimedia application examples
VOPD：Video Object Plane Decoder 10 5
357 3 70 1 2 3 4 4 16 11 S1 S2 S3
362 27
362
353 5 12 6
362 9 7 6 8 49
300 2
313 10 11
313 8 7 S4 S5 94 12
500 9 1

50. Multimedia application examples
WMD：Multi-Window Displayer 11 64 64 1 2 3 9 12 64 S7
128 96 96 3 8 4 5 6 7 96 7 2 S2 S6 S4 96 96 96 96 6 10 8 9 10 64 1 S5 4 64 11 12 5

51. Optimization II : - Predetermined Switch Mode Assignment
Key idea ：
After we applying the PACP scheme to NoC architecture, there are high opportunities for switches with the same routing state due to the communication locality.

52. We design a dual-mode crossroad switch：
Normal mode：
The switch can be controlled by request events from four-direction communication paths, and the it decides which one can use the path.
Lease-line mode：
The switch always passed signals from one path to another path by lease lines without applying arbitrations.

53. Example

54. Experimental results
Experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture.
The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.

55. Low-Power Designs for Embedded Systems The proposed Low-Power designs
Outline
Introduction
Low-Power Designs for Embedded Systems
The proposed Low-Power designs
Future interesting trends
Summary

56. Interesting topics in the future
Thermal issues
Low Power Strategies for multi-core architectures and multi-thread programming model
Electronic System-Level Design with power optimization schemes (ESL with power functionalities)

57. Electronic System-Level Design Flow (ESL)
Customer Specification
Paper Specification
HW / SW Partitioning
SystemC TLM
Concurrent HW/SW Enginering Based on TLM
Hardware Development
Verilog / VHDL
Software Development
C / C++
Co-Emulation
Test Chip
System Integration & Validation

58. ESL Design with power optimization schemes - Integrated HW / SW simulation is easy
Application
Analyzer
O.S + Compiler + IPs
Evaluation
C program
Main( ) {
Fun1();
Fun2();
………… }
Identify
Application
Characteristics
Select Primitive：
Power analysis
Partitioning
Hierarchy
Power / Performance
……….
Hardware Tuning
IP Selection
Core Library
Architecture Models
Microprocessor
Memory Architecture
Bus Structure
Encoding
Cache Organization
Peripherals
Architecture
IP1
RISC …
DSP
IPN
Software Tuning
Power-aware Library
Profiling
Code Optimization
OS scheduling policies
inst. Scheduling
Freq. Scaling
Registers Allocation ……
Memory
Peripherals
Cache
Energy Monitor
Component-based Energy
Instruction-based Energy

59. Instruction-set power data Architecture power data
ESL Design with power optimization schemes - Different views of power consumption
C Source Program
Program binary
Processor core
Source Code / Library / OS Policy view tool
Program / data memory view tool
(Inst. executes frequency, data memory)
Instruction-set view tool
(MOV, ADD, ..)
Architectural view tool
(IP, Cache, Memory, Bus, …)
Source Program
power data
Program power data
Instruction-set power data
Architecture power data No
Satisfied?
Yes
DONE

60. ESL Design with power optimization schemes - instruction-set view tool
Instruction Power (mW)
ADDC_
ADD_
ANL_
CLR_
CPL_ DA
DEC_
DIV
INC_
MOVC_
MOVC_
MOV_
MOV_
MUL
NOP
ORL_
POP
PUSH
Binaries to exercise instruction 1
Binaries to exer instruction 2
Binaries to exe instruction 3
ROM generator
Microprocessor structure
ROM entity
Simulator and power analyzer
Flat power data for instruction 1
Flat power data for instruction 2
Flat power data for instruction 3
Power data collector, structural power data translator, and display

61. ESL Design with power optimization schemes - architectural view tool
Microprocessor structure
Program binary
ROM generator
ROM entity
Simulator and power analyzer
“Flat” power data
Structural hierarchical power data translator and display
Microprocessor soft core
RT-synthesizer
ROM
1.04 mW
ALU
1.62 mW
RAM
1.42 mW
CTRL
2.69 mW
DECODER
0.07 mW
Total
7.66 mW

62. ESL Design with power optimization schemes
ESL Design with power optimization schemes - program/data memory view tool
Addr Ins Freq Pwr Freq*Pwr
00000 LJMP 1 0 0
00003 MOV_
00005 MOV_
00007 MOV_
00009 MOV_
00011 RET
00012 MOV_
00014 MOV_
00016 MOV_
00018 MOV_
00020 MOV_
00022 LCALL
Per-instruction power data (from previous tool)
Program binary
Instruction-set simulator
Program/data memory access frequencies and power (cache hits/misses rate …..)
Addr Purpose Accesses
00128 P
00129 SP
00130 DPL
00131 DPH
00144 P
00208 PSW
00224 ACC
00240 B 2598
Program hierarchy power translator and display

63. ESL Design with power optimization schemes - Source program view tool
C Source Program
Analyzer
program power data (from previous tool)
C Source program library power translator and display
Function-based Energy Information
Void main() {
mepg_decoding_t = myapi_dvs_create_thread_type(100,30,100); // Pwr = 20.3
myapi_dvs_create_thread_instance(mpeg_decoding_t, mpeg_decode_thread); // Pwr = 32.3 }

64. Imagine, if we have those GUI tools… Designers can optimize their power-aware designs easily.

65. Summary We reviewed DVS and DPM as an independent approach.
Since both approaches are based on the system idleness, DVS and DPM can be combined into a single power management framework (ESL).
You can achieve power reduction at all phases of the design cycle, but you’ll see the largest benefit at the system level, so make sure you think about power early.

66. Low-Power Design Techniques for Embedded Systems
Anytime, everywhere, low-power designs make the Earth more beautiful.
Thank you so much! Q & A