1. OpenPOWER Innovation: Redefining HPC
Bradley McCredie
VP/IBM Fellow
POWER Systems Development
President OpenPOWER Foundation

2. Price/Performance History of Computing2
Price/Performance History of Computing
Relays / Mechanical
Tubes
Moore’s Law written
Bipolar
Integrated Circuits
CMOS
Multicore
Bradley McCredie - 2/26/2015

3. Oct 10, 2003 – Expected Processor Freq Path
Bradley McCredie - 2/26/2015

4. Nov 11, 2004 – Modified Path, One Year Later
Bradley McCredie - 2/26/2015

5. Development of Commercial Aviation5
Development of Commercial Aviation
Concorde
10,000
Boeing 707
1,000
DeHaviland Comet
Speed of Sound in Air
Boeing Stratoliner
Boeing 247
Ford Trimotor
100
Aircraft Speed (mph)
DC-3
Curtiss Flying Boat 10
Innovations
1903 Powered Flight
1914 Commercial Air Boat
1927 1st Airliner
1937 Pressurized Cabins
1952 Commercial Jet Airliner
1969 Concorde Supersonic Airliner
Wright Brothers 1
1900
1920
1940
1960
1980
2000
2020
Source: F. M. Schellenberg, UCB Bodega Bay, 5

6. Source: F. M. Schellenberg, UCB Bodega Bay, 5-10-20076
Commercial Aviation
10,000
Concorde
Boeing 707
1,000
DeHaviland Comet
Speed of Sound in Air
Boeing Stratoliner
Boeing 247
747
767
A-320
777
Ford Trimotor
DC-10
MD-90
100
Aircraft Speed (mph)
DC-3
Curtiss Flying Boat 10
Innovations
1903 Powered Flight
1914 Commercial Air Boat
1927 1st Airliner
1937 Pressurized Cabins
1952 Commercial Jet Airliner
1969 Concorde Supersonic Airliner
Wright Brothers 1
1900
1920
1940
1960
1980
2000
2020
Source: F. M. Schellenberg, UCB Bodega Bay, 6

7. 425 HP 425ci Hemi 425 HP 6.1L Hemi 13 Sec ¼ mile @ 108 MPH
6.0 Sec MPH
425 HP 6.1L Hemi
13.3 Sec ¼ 107 MPH
4.7 Sec MPH 7

8. AM/FM/CD/DVD + 30G Storage + iPod Keyless Entry w/Remote Start
Navigation System, Voice Activated
Run Flat Tires (no spare)
4 Wheel Disc Antilock Brakes + Air Bags
Lighted Cup Holders, Center Console
14 MPG
FM Radio
Front Disc Brakes
Lap Belts Only
6.5 MPG 8

9. Industry Trends Generate New Opportunities
Microprocessors are no longer driving sufficient Cost/Performance improvements (Core cost/perf)
At constant technology costs
Processors
Semiconductor Technology
Three points from today’s presentation:
1) There is validated need in the industry for OpenPOWER building off of Arvind BOD of directors pitch on System Innovation
2) We are executing on pursing this opportunity through IBM led innovation that leverages both IBM (research SWG, STG, GTS) and our OPENPOWER partners efforts (we are not going it alone)
3) Our base technology is good (it is as good or better than it has ever been) and with POWER8 for the first time STG is creating disruptive system innovations that will drive results
All of this is in the context of cloud first (scale out first) there is nothing else that matters 9
IBM Confidential 9 9

10. Industry trends drive innovation beyond the chip…
Microprocessors alone no longer drive sufficient
Price/Performance improvements
Applications and Services
Firmware, Operating System and Hypervisor
System Stack
Systems Management &
Cloud Deployment
Systems Acceleration &
HW/SW Optimization
Processors
Semiconductor Technology
Moore’s Law
Processors
Semiconductor Technology
Workload Acceleration
Services Delivery Model
Advanced Memory Tech
Network & I/O Accel
Use Cases
POWER8 Linux
OpenPOWER
System stack innovations are required to drive Price/Performance
Bradley McCredie - 2/26/2015 10 10

11. Fueling an Open Development Community
Implementation / HPC / Research
System / Software / Integration
I/O / Storage / Acceleration
Boards / Systems
Chip / SOC
Complete member list at

12. Memory Interface Control
Innovation with POWER Technology
POWER
Processors
Memory Interface Control
GPU/Other
Server Class Memory
NVLINK
DMI
IBM & Partner
Devices
CAPI/PCI
Innovation with IBM and Partners is taking place on all interfaces
Wide variety of innovation strategies (Many not depicted)
Leveraging different aspects of system design
All targeting price/performance leadership
IBM Confidential 12

13. OpenPOWER Innovations Targeting HPC
Altera FPGA acceleration and IBM CAPI
Monte Carlo 250x faster than POWER8 core alone, reduced C code 40x over non-CAPI FPGA
Data Engine for NoSQL 24:1 server consolidation, 3x lower cost per user, 40TB CAPI-attached flash
CAPI dev kit with FPGA card from Nallatech
US Dept of Energy $325M super computing contract awarded to IBM, Mellanox, and NVIDIA
DoE systems for science and stockpile stewardship
Sierra and Summit systems to be >100 PF, 2 GB/core main memory, local NVRAM, and science performance 4x-8x Titan or Sequoia
Tyan OpenPOWER Customer Reference System
NVIDIA acceleration built into IBM Power S824L
8x faster than x86 Ivy Bridge on pattern extraction
82x faster for Cognos BI and DB2 BLU 13
© 2014 OpenPOWER Foundation

14. NVLink Interconnect Differences
System Hardware Design
PCIe Connection
GPU
CPU
Graphics Memory
System Memory
P8’
NVLink
40+40 GB/s
40+40 GB/s
16+16 GB/s
40+40 GB/s
Current GPU Attach Future NVLink GPU Attachment
“NVLink will help improve GPU-GPU peer-to-peer communications, eliminating the need to transfer data via the PCIe bus. It would also allow one or more GPUs to access the system RAM much quicker. The new protocol will debut in 2016 with Pascal, which was revealed to be NVidia's next GPU architecture.”

15. CAPI vs. I/O Device Driver: Data Prep
300 Instructions
10,000 Instructions
3,000 Instructions
1,000 Instructions
7.9µs
4.9µs
Total ~13µs for data prep
Typical I/O Model Flow:
Acceleration
DD Call
Copy or Pin
Source Data
MMIO Notify
Accelerator
Poll / Interrupt
Completion
Copy or Unpin
Result Data
Ret. From DD
Completion
Application
Dependent, but
Equal to below
Flow with a Coherent Model:
400 Instructions
100 Instructions
0.3µs
0.06µs
Total 0.36µs
Acceleration
Shared Mem.
Notify Accelerator
Shared Memory
Completion
Application
Dependent, but
Equal to above

16. Coherent Accelerator Processor Interface (CAPI) Overview
CAPP
PCIe
POWER8 Processor
FPGA
Accelerator Function Unit (AFU)
CAPI
IBM-Supplied POWER Service Layer
Typical I/O model flow
Acceleration
DD Call
Copy or Pin
Source Data
MMIO Notify
Accelerator
Poll / Interrupt
Completion
Copy or Unpin
Result Data
Ret. From DD
Completion
Flow with a coherent model
Acceleration
Shared Mem.
Notify Accelerator
Shared Memory
Completion
Advantages of coherent attachment over I/O attachment
Virtual addressing and data caching
Shared memory
Lower latency for highly referenced data
Easier, more natural programming model
Traditional thread-level programming
Long latency of I/O typically requires restructuring of application
Enables applications not possible on I/O
Pointer chasing, and so on

17. CAPI and Networking Opportunities

18. IBM / Mellanox / NVIDIA Collaboration Landscape
Paving the Road to Exascale with OpenPOWER Technology
IBM / Mellanox / NVIDIA Collaboration Landscape
Road to
Exascale
CUDA 5.5
CUDA 7
Open MP 4.0
CUDA 8
Open ACC
Open MP 4.0
CUDA 9
OpenMP 4.x
Programming
Model
P8 Tuleta - 4U
2 P8 (+ 2 GPU)
PCIe Gen3
CAPI
Firestone - 2U
2 P8 + 2 GPU
PCIe Gen3
CAPI
HPC Next - 2U
CAPI
NVLink
HPC Future- 2U
Enhanced CAPI
Enhanced NVLink
Air Cooled
Power Systems
HPC Future - 2U
Enhanced CAPI
Enhanced NVLink
Air/Water Cooled
Adapters
Connect-IB
(dual ports)
ConnectX-4
(dual ports)
ConnectX-5
(dual ports)
Mellanox
Interconnect Technology
Switches
FDR InfiniBand
EDR InfiniBand
HDR InfiniBand
Enhanced CAPI over
PCI-express Gen4
CPU Links
PCI-express Gen3
CAPI over PCI-express Gen3
2014
NVIDIA GPU
(GK210)
2015
NVIDIA GPU
(GP100)
2016
NVIDIA GPU
(GV100)
2017
GPUs
Chip Technology
CPU
Power8
Power8
Power Next
Power Future
JDA
NVLink
Enhanced NVLink
2014
2015
2016
2017 18 18

19. Summary
The IT industry is being disrupted and being driven by disruptions
Open hardware and open systems will be one of those disruptions
Technology innovations will come from many unpredictable places
POWER technology is well positioned to exploit these new trends