1. CESR-c and ILC Damping Ring Instrumentation
REU Student: Joseph Burrell, Wayne State University
Mentors: Mark Palmer, Eugene Tanke, John Dobbins, and Charlie Strohman
Cornell University
Laboratory for Elementary-Particle Physics

2. Instrumentation Issues for Damping Ring Studies Using CESR
Damping Ring Test Facility Instrumentation Requirements
Short lifetimes
For CesrTF at ultralow emittance, Touschek lifetimes in the several minute range are expected
Small beam sizes
typical, where b is the lattice function and e is the emittance
Short bunch spacing
3.08 ns for ILC DR
Possibly operate with 4 ns for CesrTF
June 5, 2006
2006 LEPP REU Introduction

3. Digital Readout Module Overview
Digital Motherboard
4 Analog Boards
Timing Board
I/O Transition Board
Digital Board
TigerSHARC TS101 DSP
Xilinx Virtex-2 FPGA
2 Mbytes SRAM
512 kbytes FLASH
24 MHz PLL receives CESR Timing Signal
2nd PLL produces 72 MHz on-board clock (14 ns bunch spacing)
20 ns global slew with
10 ps/step delay chips
Card delays provided by additional 10 ps/step chip
Analog Boards for BPM (button and stripline), PMT, and diode readout applications
Multi-bunch turn-by-turn readout
June 5, 2006
2006 LEPP REU Introduction

4. BPM Testing Issues Analog Board 1 e- and 1 e+ channel per board
Timing handled by independent timing blocks on timing board
512 kwords data buffers
AD8369 DVGA
600 MHz BW
-5 dB to +40 dB
AD9245 Digitizer
500 MHz BW
14 bit
June 5, 2006
2006 LEPP REU Introduction

5. Focus on BPM requirements for CesrTF
Summer Plans
Focus on BPM requirements for CesrTF
Characterization of AD8369 front ends
Detailed noise and linearity testing
Bench tests during CESR down
Beam tests using CESR BPM test stand starting in July
Verify suitability and/or modifications required for CesrTF operation in 2009
Note: this effort also supports ongoing CESR and ERL development work
In addition, participate in a general review of instrumentation requirements for CesrTF R&D
June 5, 2006
2006 LEPP REU Introduction