1. DSP技术与应用
Section 4
ADSP-2191 Memory

2. Memory Primarily Store data and instructions
Also used to access memory mapped peripherals
2191s can access External memory if present
The 2191 has a linear addressing scheme
0x to 0xFF FFFF TOTAL 16M words
Address ranges within this field define memory usage
Internal memory blocks
External Memory
2191s core access memory via the address/data busses
The DM address bus is 24 bits wide = up to 16M memory locations for data
The PM address bus is 24 bits wide = up to 16M memory locations for data and instructions
The 2191 has two other memory spaces
Boot Memory Space, IO Memory Space

4. Memory Architecture
Memory architecture supports instruction access, data access, and memory mapped peripheral accesses
Supports internal and external memory access
The ADSP-2191 has several memory spaces
Standard memory space
Data, instructions, and memory mapped peripherals
System control register memory space, use
Access specific system registers
IO Memory Space (IOMS)
Internal peripheral control and data registers
Memory mapped peripherals
Boot Memory Space (BMS)

5. ADSP-2191 Memory Map 23 TOTAL MEMORY SPACE 256, 64KW PAGES (16M WORDS)
1K BOOTROM
16-BIT
MS0
(PAGES 1-63)
MS1
(PAGES )
MS2
(PAGES )
MS3
(PAGES )
24-BIT
63K - RESERVED 23
0x00:0000
0x00:8000
0x01:0000
0xFF:0000
0xFF:0400
0xFF:FFFF
0xFF:03FF
0x00:FFFF
0x00:7FFF
TOTAL MEMORY
SPACE
256, 64KW PAGES
(16M WORDS)
EXTERNAL 16-BIT
MEMORY SPACE
(254, 64Kx16 PAGES)
INTERNAL SRAM
(PAGE 0 - DEFAULT)
INTERNAL
ROM
(PAGE 255, 64Kx24)
0xFE:FFFF
EXTERNAL MEMORY
PROGRAMMABLE
START BOUNDARIES
(MAX 64KW/PAGE)
0x40:0000
0x80:0000
0xC0:0000

6. ADSP-2191 Memory Map

7. Boot & IO Memory Space IO MEMORY SPACE EXTERNAL BOOT MEMORY (/IOMS)
(/BMS)
15/
INTERNAL
(PAGES 0-7)
256 1K
PAGES 0x
64K WORD
(BMS)
PAGES 1-254
0x00 000
0x07 3FF
0x08 000
EXTERNAL
(/IOMS)
PAGES 8-255
0xFE FFFF
254 64k pages
0xFF 3FF
IOPG8-Bit
INSTRUCTION
10-Bit

8. ADSP-2191 Memory Memory Structure
Internal memory configured for shared core & I/O accesses
I/O processor DMA transfers use ‘cycle stealing’ to access internal memory
Internal memory partitioned into 4 blocks
Supports dual data fetches
Up to two 16-bit data values accessed in single cycle (one over each bus)

9. The Modified Harvard Architecture
Data Memory Address (DAG 1)
16 Bit 24
DSP
Core
24 Bit
Program Memory Address (DAG 2) 24
Data Memory Data (DMD) 16
Program Memory Data (PMD)
Cache 24
Internal Memory
Instructions fetches are attempted every cycle over the Program Memory bus
PM Bus conflicts occur when instruction fetch and PM data fetch are required in
the same cycle (cache miss)

10. On-chip Memory Interfaces
0xC000
0xFFFF 16
Block 3 16
0x8000
0xBFFF 16 16 DM
Block 2
0x8000
0xBFFF 8 16
0x9FFF
0x8000
0x4000
0x7FFF 24
Block 1 PX 24 24
Block 0 PM
0x0000
0x3FFF
0x0000
0x3FFF 24 24
0x1FFF
0x0000
2196
2195
2191

11. PM Bus Exchange (PX) Register
Type 32 instruction reads 24 bits from address 0x Upper 16 bits are stored in AR. Lower 8 bits go to the PX register.
24-bit indirect store
Hidden 24 bit copy
16-bit on chip memory
PX is filled by zeroes
AR=PM(I4+=M5); // I4 = 0x2000
PX=AX0; // lower 8 bits
PM(I4+M5)=AY0; // upper 16 bits
AR=PM(I4+M5); // writes 8 lower bits to PX
PM(I5+M5)=AR; // reads 8 lower from PX PX 23 8 7 15 16 24 PM DM
AR=PM(I4+=M5); // I4 = 0x8000

12. LDF Segment Mapping Examples
ARCHITECTURE (ADSP-2191)
MEMORY
{ seg_inttab { TYPE(PM RAM) START(0x0000) END(0x01FF) WIDTH(24) } seg_code { TYPE(PM RAM) START(0x0200) END(0x6FFF) WIDTH(24) } seg_data2 { TYPE(PM RAM) START(0x7000) END(0x7FFF) WIDTH(24) } seg_data1 { TYPE(DM RAM) START(0x8000) END(0xFFFF) WIDTH(16) } }
ARCHITECTURE (ADSP-2196)
MEMORY
{ seg_inttab { TYPE(PM RAM) START(0x0000) END(0x01FF) WIDTH(24) } seg_code { TYPE(PM RAM) START(0x0200) END(0x17FF) WIDTH(24) } seg_data2 { TYPE(PM RAM) START(0x1800) END(0x3FFF) WIDTH(24) } seg_data1 { TYPE(DM RAM) START(0x8000) END(0x81FF) WIDTH(16) } }

13. ADSP-219x On-chip Memory Count
32kWords of 24 bit SRAM memory
32kWords of 16 bit SRAM memory
ADSP-2195
16kWords of 24 bit SRAM memory
16kWords of 16 bit SRAM memory
16kWords of 24 bit ROM optionally
ADSP-2196
8kWords of 24 bit SRAM memory
8kWords of 16 bit SRAM memory
160 kByte 1280 kBit
80 kByte 640 kBit
40 kByte 320 kBit