1. EMC of ICs Practical Trainings

2. Objectives Get familiar with IC-EMC/Winspice
Illustrate parasitic emission mechanisms
Understand parasitic emission reduction strategies
Power Decoupling Network modelling
Basis of conducted and radiated emission modelling
Basis of immunity modelling
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3. Summary IC-EMC – Reference Ex. 1. FFT of typical signals
Ex. 2. Transient current estimation
Ex. 3. Interconnect parasitics
Ex. 4. Impedance mismatch
Ex. 5. di/dt noise
Ex. 6. intrinsic decoupling
Ex. 7. added on-chip decoupling
Ex. 8. PDN modelling
Ex. 9. Radiated emission modelling
Ex. 10. Estimation of susceptibility level
Ex. 11. Susceptibility of analog input
Ex. 12. Susceptibility of output buffer
Ex. 13. Susceptibility of a micro-controller
January 18

4. IC-EMC - Simulation flow
IC-EMC schematic Editor (.sch)
IC-EMC model libraries
WinSPICE compatible netlist generation (.cir)
WinSPICE simulation
Measurement import
IC-EMC Post-processing tools (emission, impedance, S-parameters, immunity)
Output file generation 4 4
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5. IC-EMC – Most Important Icons
Open schematic (.sch)
Build SPICE netlist (.cir)
Save schematic (.sch)
Spectrum analysis
Delete symbols
Near field emission simu.
Copy symbols
Immunity simulation
Move symbols
Time domain analysis
Rotate symbols
Impedance simulation
Flip symbols
S parameter simulation
Add Text line
Ibis file editor
Add a line
Parametric analysis
View electrical net
Symbol palette
Zoom in/out
View all schematic 5
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6. IC-EMC – Link to WinSpice
Click on WinSPICE.exe
Click File/Open to open a circuit netlist (.cir) generated by ic-emc.
IC-EMC main commands (text line):
Simulation command
Command line
Parameters
Transient simulation
.tran 0.1n 100n
step + stop time
DC simulation
.DC Vdd
source + start + stop + step
Small signal freq. analysis
.AC DEC 100 1MEG 1G
sampling + nb points + start + stop
Load SPICE library
.lib 65nm.lib
Path and file name 6 6
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7. Exercise 1. FFT of typical signals
Create the schematic
Set the source generator
Transient simulation
FFT by IC-EMC
Simulate the FFT of a sinus and a square signal 7 7
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8. Exercise 1. FFT of typical signals
FFT of a sinus source
Set the voltage generator properties:
Frequency = 1 GHz
Amplitude = 1 V
Electrical model in Ex1-FFT-sinus.sch.
Ex1-FFT-sinus.sch 8 8
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9. FFT of a sinus source Exercise 1. FFT of typical signals
Type the simulation command: .tran 1n 50n
Simulate the response in time domain.
Compute the FFT.
Does the FFT result correlate with theoretical result ? 9
January 18

10. FFT of a square current source
Exercise 1. FFT of typical signals
FFT of a square current source
Set the generator properties
For example:
Period = 10 n,
PW = 4 n,
Tr = 1n, Tf = 1 n
V0 = 0 V, V1 = 1 V
Electrical model in Ex1-FFT-Pulse.sch.
Ex1-FFT-Pulse.sch 10 10
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11. FFT of a square source Exercise 1. FFT of typical signals
For a trapezoidal signal (Tr=Tf)
For a square signal (Tr=0) 11
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12. Exercise 2. Transient current estimation
Standard cell inverter in CMOS technology
Typical load capacitance
Observe in time domain the current through Vss.
Electrical model in Ex2-transient_inverter.sch.
Ex2-transient_inverter.sch 12 12
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13. Exercise 2. Transient current estimation
Time domain simulation
Adjust scales (Autofit and zoom on time axis) 13
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14. Exercise 2. Transient current estimation
What is the influence of the load capacitance (1 fF to 1 pF) ?
Ipeak
Rise time
Cload
Cload 14 14
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15. Evaluate the electrical parasitic associated to the power supply pair.
Exercise 3. Interconnect parasitics
The core is mounted in a QFP100 package.
A pair of pins is dedicated to supply the core
16 mm
7.5 mm
2.5 mm
25 µm
4.5 mm
0.7 mm
0.22 mm
Evaluate the electrical parasitic associated to the power supply pair. 15 15
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16. Exercise 3. Interconnect parasitics
Use Tools/Interconnects Parameters to evaluate R, L, C associated to package pins.
Empirical estimation :
Lead : L = 0.5 nH/mm and C = 0.1 pF/mm
Bonding : L = 1 nH/mm 16 16
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17. Exercise 4. Impedance Mismatch
Generate a fast clock
Load a transmission line model
Terminate by a high impedance
Terminate by 50 Ω
1.6mm total
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18. Exercise 5. di/dt noise
Estimate the voltage bounce on Vdd and Vss pins of the core when it is mounted in a QFP 64.
The core clock is 20 MHz.
Core noise margin ?
Electrical model in Ex4-didt_noise.sch.
Voltage fluctuations on Vdd or Vss node is equal to +/- L*di/dt = 6 nH*600 mA/150 ps = +/- 24 V.
The circuit is supplied under 1.2 V  the voltage fluctuation is 20 times larger than the nominal power supply ! However, this evaluation is unrealistic, because it supposes that all the current consumed by the circuit will flow through the package inductance. The circuit contains intrinsic capacitor which acts as a decoupling capacitor and reduce the voltage bounces.
Ex4-didt_noise.sch 18
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19. Exercise 5. di/dt noise
January 18

20. Exercise 6. Intrinsic decoupling
IC-EMC reference manual p. 18
Consider a synchronous digital core in CMOS 65 nm formed by gates with the following parameters
Std cell
Number
Typical input capa (fF)
Peak current / gate (µA)
Inverter
35000 1
120
NAND2
25000
150
DREG
20000 2
200
NOR2
For the CMOS 65 nm technological node, we can estimate that a digital gate adds a capacitor between the power supply and the ground about 5 fF. If For a digital core formed of gates, we can estimate that the core forms a decoupling capacitor about 500 pF. The accuracy of this estimation can be improved if more information about interconnects and wells are known.
Estimate the intrinsic decoupling
Estimate the dynamic current consumed by the circuit.
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21. Exercise 6. Intrinsic decoupling
Compute the on-chip noise spectrum
Ex5-IntrinsicDecoupling.sch
Electrical model in Ex5-IntrinsicDecoupling.sch
Damping effect ? 21
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22. Exercise 7. Added on-chip decoupling
IC power supply rails parasitics
Consider a 1 mm long and 40 µm wide Vdd or Vss line.
Total Inductance and resistance of chip power supply rails ?
Metal level
Thickness
Height to substrate M6
0.4 µm
4.5 µm M5
3.3 µm M1
0.3 µm
0.5 µm
Higher level of metallization are used for power supply routing. Let’s consider M5 : R = 1.1 ohm/mm, L = 105 pH/mm. 22
January 18

23. Exercise 7. Added on-chip decoupling
On-chip capacitor budget :
Is the intrinsic capacitance is sufficient to reach the noise margin target ?
How much capacitance should be added in the circuit ?
Capa. type
Capacitor density (fF/µm²)
Capa cell
2.2
Poly1 – Poly2
1.7
MIM
1.4
Theoritically, the total capacitance should be equal to 750 pF to reduce the voltage bounce under 120 mV. 250 pF should be added. In the model, the interconnect resistances tends to reduce the voltage bounce. However, they add a IR drop ! The resistance should be a little reduced.
Electrical model in Ex6-AddRonChipC.sch.
If 250 pF are added, the required size is equal to : 0.11 mm² with capa cell, 0.15 mm² with poly capa and 0.18 mm² with MIM. The area of the core is equal to 0.11 mm² (if metallization is not taken into account).
Ex6-AddRonChipC.sch 23 23
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24. Exercise 8. PDN Modelling
Impedance vs. Freq
DSPIC Z(f): find an R,L,C model
Tune to measurement file:
Electrical model in Ex7-PDNmodel.sch.
z11-dspic-vdd_10-vss_9.z
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25. Exercise 8. PDN Modelling
z11-C1nF_0603.z
1nF discrete capacitance for DPI
Impedance vs. Freq
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26. Synthesis of Exercises 1 to 8
What did we learn ?
January 18

27. Ex8-RadEmi_Config1.sch and Ex8-RadEmi_Config2.sch
Exercise 9. Radiated Emission Modeling
Near field
The circuit studied in exercise 5 is mounted in a QFP package.
Two mounting versions, depending on the power supply pair assignment (pair 1 or pair 2)
Its magnetic field emission is characterized by near field scan at 100 MHz.
Compute the magnetic field at 1 mm above the package for both configurations.
Conclude about the effect of power supply pair placement.
Scan area
Power supply pair 2
Power supply pair 1
Two configuration for power supply pair. Electrical models for each configuration in Ex8-RadEmi_Config1.sch and Ex8-RadEmi_Config2.sch.
In near field:
For pair configuration 1, Htot = -18 dBA/m for hscan = 2.7 mm above ground plane.
For pair configuration 2, Htot = dBA/m for hscan = 2.7 mm above ground plane.
In config 1, the magnetic field is reduced due to the cancellation of magnetic field generated by the circulation of current along power supply pair.
Package geometry:
Width and height = 16 mm
Package pitch = 0.5 mm
Lead frame height = 0.7 mm
Ex8-RadEmi_Config1.sch and Ex8-RadEmi_Config2.sch
January 18

28. Exercise 9. Radiated Emission Modeling
Compute the magnetic field at 1 meter above the package for both configurations.
The following table gives the limit for radiated emission at 1 meter from electronic equipment, defined by CISPR 25.
Does the circuit complies with CISPR 25 radiated limit at 100 MHz ?
CISPR 25 – Limits for narrowband radiated emission at 1 m from equipment
Class
100 MHz 1
42 dB µV/m 2
36 dB µV/m 3
30 dB µV/m 4
24 dB µV/m 5
18 dB µV/m
In far field :
For pair configuration 1, Htot = -211 dBA/m for hscan = 1000 mm above ground plane.
For pair configuration 2, Htot = dBA/m for hscan = 1000 mm above ground plane.
Limits given by CISPR25 at 100 MHz : from 42 to 18 dBµV/m  -9.5 dBµA/m to dBµA/m  dBA/m to dBA/m.
The config 1 satisfies all the classes of CISPR25, the config 2 is only compliant to class 1.
Here, only the circuit package has been taken into account. In a real case, PCB tracks, PCB planes, connectors and wires have to be taken into account to predict far field emission.
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29. Exercise 10. Estimation of susceptibility level
A RF generator produces a conducted disturbance which is injected on a 200 Ω load, though a directional coupler.
Ex9-RloadSusc.sch
Electrical model in Ex9-RloadSusc.sch.
Due to the small size of ICs, the susceptibility of an IC to EMI is usually characterized by conducted RF disturbances rather than radiated disturbances. The conducted tests are more repeatable and efficient than radiated tests.
In conducted tests such as DPI tests, a conducted disturbance is provided to a circuit pin by cables and PCB tracks, which act like antennas which couple a radiated disturbance. The conducted disturbances represent the unwanted RF-energy coupled on cable harness and PCB tracks. The susceptibility level is usually given in term of forward power delivered to the circuit. The susceptibility level depends on the circuit and pin configuration (i.e. filtering, decoupling on the pin, impedance of the pin).
Estimate the forward power to induce 1 V across the load over the frequency range 10 MHz – 1 GHz.
January 18

30. Exercise 10. Estimation of susceptibility level
Launch Susceptibility tool
Configure the RF disturbance and launch SPICE simulation
Configure the voltage criterion and extract susceptibility threshold
Display the susceptibility threshold
Typical forward power ranges from 10 dBm to 30 dBm. Corresponding to the specification of immunity level given by IEC – DPI standard.
January 18

31. Exercise 10. Estimation of susceptibility level
January 18

32. Exercise 10. Estimation of susceptibility level
Validity of the result ?
Pforward = 6 dBm
Vinc = Vload /(1+S11) et S11 = (Zload-Zc)/(Zload+Zc) = (200-50)/(200+50) = 0.6
Vinc = 1/1.6 = V
Pinc = Vinc²/Zc = 0.625²/50 = 7.8 mW = 9 dBm
 Pinc rms = Pinc/2  Pinc rms = Pinc – 3 dB = 6 dBm
January 18

33. Exercise 11. Susceptibility of analog input
A RF disturbance is conducted to an analog input.
DPI: 1 nF
PCB: short tracks
Equivalent model: see IBIS.
Susceptibility criterion : input noise < 100 mV from 10 MHz to 1 GHz.
Electrical model in Ex10-ADCInputSusc.sch.
Ex10-ADCInputSusc.sch
January 18

34. Susceptibility criterion ?
Exercise 12. Susceptibility of output buffer
The following output is loaded by a 200 Ω load and a 0.5 nF capacitance.
The susceptibility of the buffer is tested using DPI standard.
Harmonic disturbances are injected on power supply
RFI
Electrical model in Ex11-HighSideEMI.sch
Susceptibility criterion ?
Ex11-HighSideEMI.sch
January 18

35. Exercise 12. Susceptibility of output buffer
Injection on the Vdd pin
Add a 100 MHz RFI sinus signal with 2 V amplitude.
Describe the failure
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36. Square function  Non linear behavior
Exercise 12. Susceptibility of output buffer
Failure due to rectification effect.
Equation of drain current based on MOS Model 1:
Square function  Non linear behavior
January 18

37. Synthesis of Exercises 9 to 12
What did we learn?

38. Evaluation
The exam is a report to be sent back to E. Sicard & A. Boyer 3 weeks max after the end of the session. It consists in a 3-5 pages report (in English) with 3-10 figures either about:
the application of the course in your engineering work (engineers, PhD students) or
the simulation using IC-EMC of an IC case study, inspired from what was conducted during the week, either emission or immunity, with your own comments.
The evaluation is performed as follows:
1) Presentation : quality of writing, clarity of the intro, precise descriptions, conclusion, and clear figures.
2) Background : justification of the work, choice of the case study, outlines
3) Originality of work : novelty, difficulty of implementation, stages of design, simulations described
4) Summary, Prospective : synthesis of the work; limits; future work; problems; personal opinion
5) References, links : references to sources (manuals, books, papers, websites)
A transcript of records in ECTS format from INSA, University of Toulouse, will be delivered (2 credits)
January 18

39. Thank you for your attention
January 18