1. EE 595 Capstone Design Project
Depth Finder 600
EE 595 Capstone Design Project
Fall 2007
Team 3

2. Team #3: Group Members Adam Davis Tony Johnson Peter Meyer Isaac Krull
Joe Reisinger
Expertise: Digital: PLD/FPGA VHDL
Experience: Associate Applications Rockwell
Expertise: Microprocessors
Experience: Part Time Design Bucyrus
Expertise: Management Skills
Experience: Soldering, Hands-On
Expertise: Calibration, C++ Programming
Experience: Engineering Johnson Controls
Expertise: PDP, Reliability
Experience: Systems Baxter Health Care

3. Depth Finder This product will measure the depth of water.
This product uses a power supply, receiver, transmitter, microprocessor and user interface.
This application specific design will relieve the end user of difficult and hard to understand interfaces while still maintaining reliability for marine applications
This system will use a 12VDC power supply designed for marine use or 8 D Cell batteries.
This is a relatively simple design with 5 separate blocks. It utilizes our strengths as a team while still delivering key concepts learned in our academic career.

4. Performance Requirements
Functions and Capabilities
Product must be accurate to depths of +/- 5 percent of actual 60°F
-Depth in Meters must be accurate to depths of +/- 5 percent of actual depth
Product must be able to measure depths from 2 to 50 feet
-Product must be able to measure depths from 1 to 15 meters
Product must read depth continuously
Must be able to sense under the transducer within a 15 degree cone
Must be able to work both with marine batteries and with D cell batteries
Product must be able to differentiate small objects from the bottom of the lake

5. Performance Requirements
Modes of Operation
The Product shall be able to turn on and off
Power Inputs
The battery must be able to last for 5 hours on full operation without recharge
The product must be able to operate on a standard 12 V marine battery
The product must be able to operate on 8 standard D Cell batteries
Electrical Functions
The product must be able to operate within a voltage range of V
Operator I/O Inputs
The On/Off switch must be a momentary off pushbutton switch
The Feet/Meter switch must be a momentary off pushbutton switch
The Feet/meter display must be a 7 segment LED.
The display must be 0.75 in by 1.48 in.
The display must be readable up to 5 feet.
Mechanical Interfaces
The product must be able to mount onto an L bracket

6. Standard Requirements
Environment & Safety
The product shall be able to operate in temperatures between 0 and 55 degrees Celsius
The product shall be able to operate in 0-90% non-condensing humidity
The product shall be able to operate in altitude ranges from sea level to 8000 feet
The product shall be able to be stored in temperature ranging from -6 to 65 degrees Celsius
The product shall be able to be stored in 0-90% non-condensing humidity
The product shall be able to be stored in altitudes ranging from -500 to feet
The product shall be able to be stored without operation for 10 years
The product must be able to be immersed in water for no more than 5 seconds and still be able to operate correctly.
In the event of submersion for longer than 5 seconds, the device shall fail in a manor as to not cause bodily injury.

7. System - Std Reqs: Market & Business Case
Requirement Units to Specify
Competitors
Market Size
Average List Price
Market Geography
Market Demography
Intended Application
Material Cost
Manufacturing Cost
Annual Volume
Humminbird, Lowrance, Eagle, Garmin.
10M
$150
USA and Canada
14- up, Male and Female
Marine
$57
$67
10000 Units/yr

8. Refined Block Diagram Key Power Analog Signal Ping Signal
Push Button #1
Push Button #2
LED Display
Backlight for label
Control
Ultrasonic
Transmitter
9 V
Peter
Vcc=9 V
Power Source
10 – 14.8 V
Joe
Ultrasonic
Receiver
5, 9 V
Isaac
CPLD 5V
Adam
Vcc = 5 V
Vcc = 9 V
Vcc=5 V
User Interface
5 V
Tony

9. Refined Block Diagram Description Table
Block Name
Owner
Brief Description
Of Block Function
Power
Interfaces
Digital
Analog 1
Power Supply
Joe Reisinger
Converts VDC to 5VDC and 9VDC with minimal ripple
In: VDC
Out: 5VDC,
9VDC
None
Out: Vbat 2
CPLD
Adam Davis
CPU design using CPLD
Clock determined by required time delay
In: 5VDC
Out: User Interface
In: Push Buttons
In: Input from Transducer circuit 3
User Interface
Tony Johnson
Allows the user to interface with the device, including display of depth and push buttons for options
In: 5VDC
In: CPLD
Out: Push Buttons 4
Transmitter
Peter Meyer
Transmits a signal into the water for reflection detection for the receiver
In: 9VDC
Out: Signal
In: Signal from CPLD 5
Receiver
Isaac Krull
Receives signals from the water and sends the corresponding signals to the CPLD
In: 5VDC, 9VDC
Out: Signal to CPLD

10. Block Signal Table: Power

11. Block Signal Table: Digital

12. Block Signal Table: Analog

13. Ethical/Societal Issues
Our depth finder is at risk of electrical faults and possible electrocution if proper procedures to eliminate these risks are not taken.
Our unit will need to be enclosed in a waterproof enclosure.
Proper safety grounds must also be implemented.
These actions will greatly reduce the risk of possible electrical faults or electrocution.
The engineering of our sonar transmitter and receiver is the most critical part of our product.
If this isn’t functioning 100% correct, the product will be useless.
To ensure this area of engineering is 100% correct numerous extensive tests will be performed on the transmitter and receiver components.

14. Applicable Patents
Name: Portable Fish Finder Patent Number: Date: September 14, 2004
This patent could be designed around if we intended our unit to be permanently used on a boat and not portable. A different mounting device other than a suction cup could be used to mount the transducer to the boat.
Name: Method for determining depth values of a body of water Patent Number: Date: November 14, 1995
This patent could be designed around by omitting the velocity sensor used and assume the velocity of the sound signal to be relatively constant. For averages lakes, the velocity will not vary greatly with the change in depth. The depth our depth finder is designed for won’t be affected by changing velocity due to depth.
Name: Depth Finder having variable measurement capabilities Patent Number: Date: November 11, 1991
This patent could be designed around by utilizing a different display than a liquid crystal display. A typical CRT display or LED display could be used instead. Also, our depth finder would be designed for use in fresh water only.

15. Burns from Hot, Touchable Surfaces
Mitigation Design/Devices/Materials/Packaging
In the event of failure, the battery and power supply shall be isolated from the user with some sort of protective cover.
Affected Blocks
Power Supply
Test(s) Required to Verify Protection
Continuous use and thermal testing

16. Unsafe Single Point/Device Failures
Mitigation Design/Devices/Materials/Packaging
In case of device failure, an audible alarm will sound
Materials shall be of non-corrosive, thermal treated material
Affected Blocks
User Interface, Transducer, CPLD
Test(s) Required to Verify Protection
Induce a failure during normal operation
Conduct environmental testing on prototype materials

17. Electric Shock Mitigation Design/Devices/Materials/Packaging
The user interface will be isolated by using dielectric materials.
Grounding and low potential at all conductive surfaces.
Insulation of high voltages
Affected Blocks
User interface
Power Supply
Transducer Circuit
Test(s) Required to Verify Protection
Electrostatic Discharge Testing to 15kV
Surface voltage potential sensing at all high voltage contained components

18. Abusive Or Unknowing Users
Mitigation Design/Devices/Materials/Packaging
Utilize warning labels on the device and user manual to not allow children to use the device.
Design a carrying case which is lockable to prevent unwanted use by children.
Allow the operation of push buttons at required time intervals throughout the use of the CPLD/software
Affected Blocks
CPLD
Test(s) Required to Verify Protection
Random button pushing

19. Sharp Edges & Pinch Points
Mitigation Design/Devices/Materials/Packaging
All corners and edges will be rounded. Warning indications will be documented in the user manual and near any trouble spots.
The battery cable will consist of pinch proof connectors. Also, the user interface will consist of push buttons rather than switches.
Affected Blocks
User Interface, Power supply
Test(s) Required to Verify Protection
Physical inspection

20. Magnetic Field Energy Mitigation Design/Devices/Materials/Packaging
Twisted shielded cables
Affected Blocks
Transmitter and Receiver
Test(s) Required to Verify Protection
Magnetic Field Immunity

21. Electro-Static Discharge
Mitigation Design/Devices/Materials/Packaging
Electronic shielded enclosures
Ground coupled user inputs
Affected Blocks
User Interface
Test(s) Required to Verify Protection
ESD Immunity Test

22. RF Electric Field Energy
Mitigation Design/Devices/Materials/Packaging
RF shielded signal cables
Affected Blocks
Transmitter, Receiver, CPLD
Test(s) Required to Verify Protection
RF Conducted Immunity

23. Interference with Other Electronic Systems
Mitigation Design/Devices/Materials/Packaging
Fuse to isolate power supply
Affected Blocks
Power Supply
Test(s) Required to Verify Protection
Power Surge Immunity Test

25. Block Prototyping Plan Template
Name
Block Area (cm2)
Board #
Board
Substrate
Type
Comp
Attachment
Board Dimensions
(cm x cm)
Types of
Connectors
CPLD
2.413x1.5875 1
PCB
Through Hole
9.652x6.35
Trace
U/I
4.826x3.175
Power Supply
3.413x1.5875
Trace/Pad
Receiver 2
Transmitter
4.826x3.715

26. Block Description and Purpose Slide Power Supply
The power supply will consist of a battery pack containing 8 D-cell batteries. Also, it will be capable of connecting to a 12V marine battery.
It will contain a 5V regulator needed by the CPLD, Display, and Receiver blocks
It will contain a 9V regulator needed by the Transmitter and Receiver block
A transformer will drive the transducer
A transistor, supplied by 12V, will act as a “switch” for the transformer.
The purpose of this block is to supply all blocks with the voltage necessary to perform their functions.
Powers the transducer and helps to provide a means of portability.
A 4 amp max current will be supplied.
The On/Off switch for power will be located on the display.

27. Standard Requirements
Max Operating Temp Range: 0C to 55C Operating Voltage Range: 10.0V to 14.8V Power Source: D-Cell Batteries Max Product Volume: 500 cm^3 Max Mass: kg
Performance Requirements
Power Modes: On (+12V), Off Min Current Requirements: 5V: 410 mA V: 160 mA V: 2 A Maximum Current Supply: 4A Transducer Supply Voltage: kHz Receiver Supply Voltage: 5V

28. Block Signal Input/Output Summary Power Supply

29. Block Diagram Breakdown Power Supply
Transmitter Input
Transistor to
Power transducer
Marine Battery
5V Regulator
To User Interface, CPLD, Transmitter/Receiver
Switch
+12V
D-Cell Battery Pack
To Transmitter/Receiver Circuit
9V Regulator

30. Block Preliminary Schematic Power Supply
+12V supply
+9V, +5V regulated
AC signal generated from transmitter pulses
Step-up transformer to drive transducer
Need to drive 150V transducer after transmitter pulses to “listen” for return signal.

31. Block Preliminary Bill of Materials Power Supply

32. Block Detailed Design Calculations & Component Selection
All components are to be thru-hole. This allows for easier prototyping.
Bypass capacitors are added to both sides of each regulator for decoupling.
The voltage regulators are of TO-220 package. They are cheap, heat sinkable (in case too much current), and easily mountable
5V: 7V*.750A (max) = 5.25W Using a 20W regulator
9V: 3V*.5A (max) =1.5W Using a 5W regulator
Safety Devices: Fuses, especially for the transducer which has a high current draw.
+12 V supply ~2A in operation, +9 V supply ~160mA
 4A fuse
+5 V supply <500mA from display, ~10mA from microprocessor, ~250mA to other board
1A fuse
Transistor
2A will flow across the transistor during operation.
The transformer will be supplied 5V, leaving 7V VCE
2A*7V=21W
The transistor is rated up to 75W
Transformer
5V input
Need 150V out to secondary

33. DFM Calculations Power Supply

34. Transmitter Block Description and Purpose
The purpose of this block is to provide the signal to drive the transducer
Takes DC voltage and turns into 50 kHz square wave
Square wave is transformed into a sine wave. The sine wave is amplified and then drives transducer

35. Performance Requirements
Transducer must be in a water-tight enclosure
Must receive between 4.5 and 18 Volts from the power supply
Transducer power supply must be able to generate 16 pulses at 50kHz, and shut off until the pulse is received back.
Amplifier must take approximately 6 V at 200mA, and convert it to the transducer bias voltage of 150V

36. Block Diagram Breakdown Slide
50 KHz Signal Generator
Amplification
Circuit
From Power
From CPLD:
Control for how
Long signal is
generated
50 kHz Ultrasonic
Transducer
To CPLD

37. Block Preliminary Schematic

38. Theory of Operation LM555 timer chip generates a 50 kHz square wave
Disable pin allows CPLD to control periods of signal generation
Second-order low-pass filter removes harmonics to create a more sinusoidal signal
Sine wave drives the base of a transistor to power the transducer

39. Important Equations

40. Equation Solutions Ra arbitrarily chosen as 1 kohm C = 1 nF
f = 50 kHz = 1.44/[(Ra + 2Rb)C]
Rb = 13.9 kohm
THIGH = (.693)(Ra + Rb)(C) =
* 10-5
TLOW = (.693)(Rb)(C) =
9.63 * 10-7

41. Preliminary Bill of Materials
National Semi-Conductor LM555 Timer Chip
RS ¼ Watt, 5% Tolerance Resistors
.01uF Capacitor
1 nF Capacitor

42. Part Rationale LM555: Ability to create necessary frequency signal
Ability to be shut off from outside source
Stable operation between 4.5 and 18 Volts
Running temperature range (0-70 degrees C)
Small package type: DIP8
Low-Cost : $1.69 individual cost

43. Part Rationale RS 271-280 Micro-Size Potentiometer Compact size
Availability
Easily tunable prototype
Low-cost: $1.49

44. Package Type Rationale
RS ¼ Watt, 5% Tolerance Resistors
Power ratings meet needs: Typically can handle between 200 and 250 Volts. They will not see more than 150 V.

45. Block Signal Input/Output Summary Transmitter

46. Analog Block DFM - Passive Discrete Table
Worst-Case: Square Wave Generator
f = 1.44/[(Ra + 2Rb)C],
Ra= , Rb= , C=9.9e-10 – 1.01e-9
f = kHz
Worst-Case: Low-Pass Filter
fb = 1/[6.283(R2C2)1/2
R = , C = 9.9e-9 – 1.01e-8
fb = kHz

47. Receiver
Purpose
The receiver block will amplify an input signal from a transducer. This amplified signal will than be fed into a tone decoder which will swing low when the specified signal is detected. This low will then go into a voltage comparator to give the microprocessor a clean signal.

48. Receiver Block Standard Requirements
The receiver block must be able to amplify a signal from +/-5 mV pk to 5 V pk for input into the tone decoder.
The output must produce a 0 V dc level , 0-800mv and 2.5 to 5V for logic high, for input to the CPLD.
Standard
Temperature range C
Max current mA
Voltage rating – 5.5 V

49. Receiver Block Performance Requirements
-The amplifier block will amplify a signal from the transducer to a .2 – 4.5 V signal for input to the tone decoder
- The logic low from the tone decoder must be less than 2.5 v, and have a fall time of less than 50ns.
- The logic High must be greater than 2.5 volts and have a rise time less than 200 ns

50. Receiver Block Performance Requirements
- The comparator block will be configured to account for a .25 V hysteresis
- No potentiometers will be used in the circuit all resistor values will be calculated based on the 50 kHz signal

51. Block Signal Input/Output Summary Receiver

52. Receiver Block Diagram

53. Receiver Schematic

54. Receiver Schematic
A buffer will be placed before the amplification block
The LM 311 will act as the voltage comparator ensuring a dc logic low
150 mA fuses will be added on the 5V power and 9V line to protect the Tone decoder and other ICs

55. Receiver Design Calculations & Component Selection PLL Equations
Fo = 1 / (1.1 x (25k) x .001uf)
BW = 1070 x sqrt (vi / (fo x .02 uf)
+/- 5 khz
Other capacitors on diagram are bypass caps
Resistor values were chosen for desired gain

56. Receiver Considerations
There is a 30 ns fall time and 150 ns rise time on output of decoder
Fo will change +\- .1 % for every 1 degree change in temperature.
Bandwidth with change .05% for every 1 degree temperature change

57. Receiver Prototype Cost
7 resistors $.10
2 variable resistors $.75
LM741 $.84
LM311 $.55
LM567 $1.27
4 ceramic capacitors $.15
Total parts cost $4.91
**** All parts are through hole

58. Receiver DFM

59. User Interface / Display
Purpose: Creates an interface with the CPLD to display the depth being read. The display also has the capability to switch the output of the CPLD between English and metric.
The display is a 7 segment LED display with a common anode. The common anode is connected to +5 volts. The cathodes are connected to the CPLD along with a current limiting resistor for each individual LED. The CPLD grounds applicable signals to light up certain LED’s corresponding to the correct depth reading.

60. Standard Requirements
Max Operating Temp Range: 0C to 55C Min Operating Voltage Range: 4.75V to 5.25V Maximum Current Draw: 250mA
Performance Requirements
Power Modes: On / Off / Error Display Type: 7 Segment LED Display Char Matrix: 3 Char./Row, 1 Row Display Size: cm x 3.78cm Switch Type: On / Off Pushbutton

61. Block Signal Input/Output Summary User Interface

62. Block Diagram of U/I + 5V CPLD Resistor Array LED Display
English/Metric Pushbutton
On/Off Pushbutton
CPLD
English/Metric
Backlight
2 Wire Array
Resistor Array
LED Display
22 Wire Array
22 Wire Array

63. User Interface Schematic
Common Anodes connected to +5v
CPLD grounds cathode to illuminate LED’s
Current limiting resistors
Momentary on pushbuttons

64. User Interface Block – Bill of Materials
(1) - 7 Segment LED Display – LDT-A512RI
(3) ohm, 250mW 8 Resistor Array – 4116R-1-271LF
(2) – 150 ohm, 125mW resistor, axial
(2) – 2x5mm Rectangular LED – SSL-LX2573GD
(2) – Momentary SPST NO Push button – D6R60 F1 LFS
(1) – 0.1uF Ceramic Capacitor

65. Calculations / Component Selection
Device Package Type: 28-Dip 7 Segment LED LED Forward current: Typical 10mA LED Forward voltage: 2.2V Typical, 2.6V Max Source Voltage: 5V Current Limiting resistor: (VS-VLED)/270Ω (+/-2%)=If If = 10.37mA @ CPLD Vol max (0.5V) and Max forward voltage If = 8.51mA CPLD IoL (max) = 24mA PCB Trace Width: 0.010” (0.3 A max)
270Ω was chosen as the current limiting resistor to produce a forward current slightly above 10mA under typical operating conditions There is no minimum current needed to drive the LED’s, but the lower the current the dimmer the LED’s. 10mA is the ideal brightness.

66. Calculations / Component Selection
Device Package Type: SMT1210 LED LED Forward current: Typical 25mA LED Forward voltage: 2V Typical, 2.6V Max Source Voltage: 5V Current Limiting resistor: (VS-VLED)/150Ω (+/-5%)=If If = 20mA @ CPLD Vol max (0.5V) and Max forward voltage If = 12.7mA CPLD IoL (max) = 24mA PCB Trace Width: 0.010” (0.3 A max)
150Ω was chosen as the current limiting resistor to produce a forward current of 20mA under typical operating conditions There is no minimum current needed to drive the LED’s, but the lower the current the dimmer the LED’s. 20mA is the ideal brightness.

67. User Interface DFM

68. CPLD – Definition
This block shall maintain the safety of the device as well as the primary state control.
The block will control the transducer circuit as well as all the operator interfaces.
The block will convert the time intervals from send to echo and produce a numerical value of depth on the user interface.
This block will also control the power state of the product via a push button input to the CPLD

69. CPLD – Standard Requirements
Must be comparable in cost to other manufacturers (Associated)
Must be able to send depth value to seven segment displays (Associated)
Must be able to withstand glitches from other blocks (Associated)
Design to minimize battery consumption (Allocated)

70. CPLD – Performance Requirements
Must be accurate to within 5% of total depth (Associated)
Must be capable of measuring depths up to 50 Feet (Associated)
Design to work with relatively noisy signals from transducer circuit (Associated)
Design to incorporate error mode to ensure safe operation when not retrieving a signal (Associated)
Be somewhat shock resistant for marine and portable use (Associated)

71. Block Signal Input/Output Summary CPLD

72. CPLD Block – Block Diagram
Output to 7-Segment Display
22 Sinking Outputs
Output to Meters/Feet LED’s
2 Sinking Outputs 22 2
From Power Supply
Power Input
Filtering
Main
Processor
CPLD
Input from User Interface
2 5V Logic Inputs
Power Supply to Processor
Clock
Input from Echo Receive Circuit, 5V Logic Input
Output to Transducer Transmit Circuit
1 Sinking Output

73. CPLD – Schematic
All disconnected pins are unused in the design. CPLD will disregard these I/O

74. CPLD – Bill of Materials
(1) - Lattice Semiconductor CPLD – M4A5 32/64
(3) - .1 uF Ceramic Capacitors
(1) – 555 Timer National Semiconductor – LM555CN/NOPB
(1) – 2.94k Ohm Resistor Yegeo – MFR-25FRF-2X94
(1) – 100 Ohm Resistor Panasonic – MFR-25FRF-100R
(2) uF Ceramic Capacitors Epcos – B37981M1103K000

75. CPLD – Bill of Materials Detailed Design Calculations
- CPLD Selection
Requires clock speeds above 10kHz
Requires up to 32 input/Output pins
Requires minimum of 16 Registers
*Selection based on this material, Lattice Semiconductor M4A5 line best suited for application while still remaining a low power device
-Capacitor Selection for Power Supply Inputs
Requires .1 uF capacitance
*Selection based on this material, devices are easy to find and readily available
-Resistor Selection for Key Timing Parameters
Requires 1% accuracy
*Selection base on this material, any high accuracy resistor shall be suitable
-Capacitor Selection for Key Timing Parameters
Requires .01 uF capacitance

76. CPLD – Bill of Materials Detailed Design Calculations for Clock Circuit
- Required clock speed of kHz is necessary to obtain depth accuracy at 60 °F
- 555 Timer Calculations
Generated Clock Speed Calculation
Freq = 1.44/(R1 + R2 * 2) * C
24.07kHz = 1.44/ * 2) * .01 e-6
- Effect of Component Tolerance Errors
Highest Frequency = kHz = 2% error in depth
Lowest Frequency = kHz = 2% error in depth

77. CPLD Theory of Operation
The CPLD shall control the states of the device as well as control transmitter circuit and user interfaces
The depth will be figured by using multiple BCD counters in series. The clock speed for the CPLD is configured for which each clock pulse = 1 ft of depth.
The CPLD will determine the time from sending the signal to receiving it back, this time is counted on the BCD counters and is latched to the output LED’s once the Echo signal is received.
BCD Counters will also determine Timeout (S) and Timeout (L)

78. CPLD Theory of Operation (State Diagram)
Echo Receive (OR) Timeout (L)
Idle Feet
Send Feet
Receive Feet
Timeout (L)
Timeout (S)
Power Sw.
Power Sw.
Power Sw.
Units Sw.
Power Sw.
Units Sw.
Off
Units Sw.
Units Sw.
Units Sw.
Power Sw.
Units Sw.
Power Sw.
Power Sw.
Idle Meters
Send Meters
Receive Meters
Timeout (L)
Timeout (S)
Echo Receive (OR) Timeout (L)

79. DFM Analysis for Digital Devices

80. CPLD Block Passive Components

81. Printed Circuit Board #1

82. Printed Circuit Board #2

83. Overall Mfg Process Diagram
Setup
Screen
Print
Placement
Reflow
Wash
Hand
Placement
Inspection
In Circuit
Test
Stress
Screen
Functional
Test
Pack/Ship

84. Manual Insert Manual Solder
Through Hole
LED Display
Momentary Off Pushbutton
17.5 Kohm resistor
CPLD Socket
Non PCB Mounted
D-Cell holder
Transducer
MTA Connectors

85. Depthfinder 600 Production BOM