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Logical Design of Digital Systems
Introduction Logical Design of Digital Systems Summer Semester 2017
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Lectures/ExerciseLab: Dr.-Ing. Stefan Werner / Uwe Dippel
Lecturers Lectures/ExerciseLab: Dr.-Ing. Stefan Werner / Uwe Dippel Stefan Werner room BB 313/ Tel: 0203/ Uwe Dippel room BB 315a/ Tel: 0203/
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Mandatory for ISE Bachelor 2nd Semester
Organisation Mandatory for ISE Bachelor 2nd Semester Computer Science & Communications Engineering (PO 08) Computer Engineering (PO 08) Computer Engineering (Software Eng.) (PO 15) Computer Engineering (Communications) (PO 15) Electrical & Electronics Engineering (PO 15) Can be chosen as elective for B.Sc. ISE (no lab) B.Sc. Wirtschaftsingenieur (no lab) B.Sc. Elektro & Informationstechnik (no lab) B.Sc. Medizintechnik (no lab)
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Logical Design of Digital Systems Sequential Circuit Design
Requiremets You should have completed Fundamentals of Computer Engineering Logical Design of Digital Systems Sequential Circuit Design Fundamentals of Computer Engineering Flip-Flops/ Moore Machine/ Mealy Machine Combinatorial Circuit Design KV-Minimization Boolean Algebra/ Boolean Functions
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Testing digital circuits
Content of LDDS Testing digital circuits Logical Design of Digital Systems Elementary sequential circuits/ sequential circuit design Algorihmic minimization approaches Memory Units and programmable logic devices Elementary combinatorial circuits combinatorial circuit design Short Repetition of FCE Fundamentals of Computer Engineering
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Schedule Lectures: Thursdays 14:45-16:15 s.t. Room SG 135 Lecturer: Dr.-Ing. Stefan Werner Exercises: Thursdays 16:30-17:15 s.t. Room SG 135 Lecturer: Dipl.-Ing. Uwe Dippel (start: ) Tuturials: Thursdays 13:00-14:00 Room BA (start: ) Language: English Exam: English (closed Book/ Multiple Choice) Lectures Website: Download Lecture slides and exercise sheets Lecture notes (2009)
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Semester Schedule
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English Books Moshe Morris Mano; Charles R. Kime: Logic computer and design fundamentals; Pearson Prentice Hall, [YGQ 4264] B. Holsworth: Digital Logic Design; online access via university library. Tocci R.J.; Widmer N.S.: Digital Systems, Prentice Hall, 2001 [45-YGQ 1436] Roth, C.H.: Fundamentals of Logic Design PWS Publishing Company, 1995 [45-YGQ 4426]
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German Books Hoffmann,D.: Grundlagen der technischen Informatik Carl Hanser Verlag 2007 [45 TWG 40340] Liebig, H.: Logischer Entwurf digitaler Systeme, 3. Auflage, Springer 1996 [43 YGQ 3420] Almaini, A.E.A.: Kombinatorische und sequentielle Schaltsysteme Prentice Hall, [43-YGQ 3030] Eschermann, B.: Funktionaler Entwurf digitaler Schaltungen; Springer 1993 [43 YGQ 3632] Wojtkowiak, H.: Test und Testbarkeit digitaler Schaltungen; Teubner 1988 [43 YGQ 2474] Daehn, W.: Testverfahren in der Mikroelektronik; Springer 1997 [YGQ 3535] Bertz, B.: Elektroniksimulation mit PSPICE Vieweg und Teubner 2007 [45 YCH 1605]
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Tutorials
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Tutorials Extra Offer: Thursdays: 13:00-14:00 Room: BA Attandance is free of choice No credits Starts: April 27th
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Tutorial Tutorial is brought to you by senior students aims at giving more examples More interactive than lectures and exercises Allows more flexibility in speed and topic Gives feedback by homework and intermediate trial exam Styles can vary from week to week
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Good arguments to attand the Tutorials
Success/failure rate in LDDS Exam (SS 2016) All students Only students who didn‘t attand any tutorial Only students who attand min.3 tutorials and trial exam
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Lab Organisation
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Lab is Mandatory for ISE Bachelor 2nd Semester
Computer Science & Communications Engineering (PO 08) Computer Engineering (PO 08) Computer Engineering (Software Eng.) (PO 15) Computer Engineering (Communications) (PO 15) Electrical & Electronics Engineering (PO 15) Erasmus and Exchange with Learning Agreement All others: there are not enough free places this year
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Registration is mandatory Registration is possible ONLY online
Lab organization Registration is mandatory Registration is possible ONLY online Registration: open from April, 18th -25th Schedule and group organisation: done by Institute of Computer Engineering (in exceptional cases suggestions can be made before April 25th (16:00) by to after that date, no changes in group assignment or scheduling are possible) will be published on April 28th (at latest)
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Lab experiments: start May 2nd
Lab organization Lab experiments: start May 2nd NOT all groups have to come on all days. Please refer to group assignment and group scheduling for your individual lab schedules. Group assignement and group scheduling will be published on April 28th (at latest) Anyway, all of you should be be prepared as if you would start on May 2nd.
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Website http://ti.uni-due.de/ti/de/education/teaching/ss17
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Equipment for analysis and testing of digital circuits
Lab syllabus Systems of high practical relevance are introduced to the students in the lab. The simulation system OrCAD, which is used to analyze memory- and bus-components, especially their timing behavior Hard- and software tools for the development of programmable logic devices Equipment for analysis and testing of digital circuits
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Lab Schedule Day: Mondays/Tuesdays 8:00-12: Frequency: (planned) every 3 weeks/ 4 Experiments Room: BB Organization: groups of 2-3 students Lab begins: May 2nd Language: English Lab attandance and successfull completion is mandatory to receive all credits
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Lab Attendence Successful lab attendance of ALL Experiments is mandatory to receive all credits for the lab. Successful lab attendance will be documented on your lab attandance sheet (cover sheet of lab manuals) by Passing the Antestat (short multiple choice test by the tutors PRIOR to the experiment – student need to be prepared!) Lab attandance (tutors‘ signature) Lab review (Abtestat) (short test on overall lab) You must pass ALL parts, attend ALL experiments to pass the lab!! Students are allowed to repeat only one lab
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Lab conduction Bring your lab manuals to every experiment In your own interest: get the tutor‘s signatures for your passed Antestat and attended experiment There might be preparation tasks which you have to answer prior to the lab !!!!!
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Microprogramming / ROM Logic analysis and circuit testing
Lab Content Experiment 1: Bus Circuits Experiment 2: Microprogramming / ROM Experiment 3: Programmable Logic Experiment 4: Logic analysis and circuit testing
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