1. Miguel Angel Quero Corrales
Study and development of a PLC-based controller for Vacuum valves and their interlocks
Miguel Angel Quero Corrales
TE-VSC-ICM
Vacuum, Surfaces & Coatings Group
Technology Department

2. Miguel Angel Quero Corrales
Index
1. Temporal response characterization.
Characterization of vacuum controllers for
Characterization of Interlock crates.
Characterization of valve controllers (SVCU).
Conclusions.
2. Prototype development based on Siemens PLC
3. Future Work
VGPs
VPIs
LHC
SPS
CPS
LHC
SPS
CPS
Miguel Angel Quero Corrales

3. Miguel Angel Quero Corrales
Motivation
Characterize the response of all devices in the existing interlock chain
CPS, SPS and LHC
Evaluate which element introduces the most latency
Propose possible improvements concerning VVGS & interlock controllers:
common system for more flexibility, easy maintenance
new technology (obsolescence of the current system)
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4. 1. Temporal response characterization
Miguel Angel Quero Corrales

5. General diagram of the current VVGS interlock chain
TN-NETWORK
VGP
VPI
This is a basic diagram of all the different devices used in the interlock chain. In here, the gauges and pumps ( VGP and VPI) are connected to the corresponding controllers (TPG 300 and the VPI’s power supply). Theses are configured according to a predefined pressure or voltage threshold. This threshold defines the moment in which the pressure level is above accepted and therefore, the corresponding Sector Valve should be closed to prevent propagation of pressure rise. The interlocks crate serve the purpose of implementing the local interlocking logic for each valve and the SVCU crate gathers all these signals and processes them as an ensemble.
Master PLC connection via Technical network to main SCADA
VGP - Penning Ionization gauge.
VPI - Vacuum Ion Pump
SVCU - Sector Valve Control Unit
VVGS - Vacuum Sector Gate Valve
PLC - Programmable Logic Controller
Miguel Angel Quero Corrales 4

6. Delay characterization of VGP/R controller (TPG300)
SourceMeter
Oscilloscope
Power Supply
TPG300
PIN 8
SMU
(Voltage source)
PIN 7
24 V + -
- Pressure threshold: 1⋅10E-6 / 4⋅10E-6 mbar
Input : 27 mV and 115 mV (2.7 μA and 11.5 μA)
- Cards used: PE 300T11 & PE 300DC9
- Filter time constant: Fast, Medium, Slow
Most common configuration
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7. Delay characterization of VPI controllers
Hand unit
LHC/CPS VPI controller
SourceMeter
Oscilloscope
Power Supply
Multimeter
SMU
VPI controller
Hand unit 
0-10 V Output voltage
Multimeter
Shunt
Relay output
Name
Type I
1-2·10-6 mbar
V = 40⋅I [mV]
VPIA/VPIAN
30l/s 1 40
VPIB
Varian Starcell 75 (60l/s) 3
120
VPIZ
Varian triode 350l/s 7
280
VPIC/VPICA
Varian Starcell 400l/s 20
800
VPIY
VacIon Plus 500 Starcell (400l/s)
Miguel Angel Quero Corrales

8. VVGS Interlock logic for CPS
Miguel Angel Quero Corrales

9. VVGS Interlock logic for SPS
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10. VVGS Interlock logic for LHC
EPROM
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11. Delay characterization of Interlock crates
CPS
Input from VPI
24 V A D C B
SPS
LHC
Miguel Angel Quero Corrales

12. Delay characterization of VVGS controllers
VVGS controller (SVCU)
INTL signal
RVVGS
Miguel Angel Quero Corrales

13. Final results and conclusions
Elements that generate the most delay in the interlock chain:
TPG 300 for LHC.
SVCU crate for SPS and CPS
Aprox. latency: hundreds of milliseconds
Possible replacement for a system that allows homogeneization and flexibility in the logic (at least with the same latency):
PLC solution
Very accesible, extended in the industry and largely supported and developed.
Extremely modular and flexible.
Longer life cicle.
Accelerator
Total average delay [ms]
LHC
774
SPS
360
CPS
228
Miguel Angel Quero Corrales

14. 2. VVGS & interlocks control system based on PLC
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15. Proposed configuration
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16. Miguel Angel Quero Corrales
Pros & cons
Remote IO crates (ET200SP+CPU)
Pros:
Hardware modularity and flexibility (e.g. if new controllers are implemented, if the layout is changed, etc).
Software flexibility (e.g. if the logic of each interlock chain is changed).
Tested reliability of the hardware on industry.
Remotely monitoring of all the signals when SCADA application is integrated.
Part of the current cabling could be removed using PROFINET field bus.
Cons:
Software updates may be needed (change of local behaviour or logic): all outputs will be off (VVGSs will be closed).
- Possible shutdown: control loss. Watchdogs and security meassures will need to be implemented.
Miguel Angel Quero Corrales

17. PLC choices. Cost estimations and considerations
Only MP and SP offer fast-wiring (push-in type)
Only S and SP can fit in a 3U EUROPA crate
SP offers the biggest signal density and the most compact solution
SP’s framework is the cheapest !!!
Miguel Angel Quero Corrales

18. Proposed hardware architecture. Remote IO crate
Direct connection to Interface crates.
24 V Power Supply
Up to 3 of each interface crate : control of up to 24 VVGS + AUX.
Direct connection to DI/DO modules (fast-wiring)
Miguel Angel Quero Corrales

19. Proposed configuration
RING architecture
Other configurations also thought: no CPU in Remote IO. VVGS control in the Masters’ PLC: redoing the code of it in order to control VVGS plus slowest. With CPU. But HMI only in master. Less local control.
Miguel Angel Quero Corrales

20. Miguel Angel Quero Corrales
Pros & cons
Interface crates
Pros:
More density of connections: less Remote IOs per point and better identification of equipment.
Flexibility and modularity in the architecture.
DC/DC isolation via optocouplers for VVGS and vacuum controllers.
Cons:
Costly replacement of big cabling when needed.
Disconection of cable to Remote IO crate would mean loss of feedback of interlock or VVGS status and control.
Miguel Angel Quero Corrales

21. Interlock Interface crate and cards
Direct connection to the Vacuum controllers (TPG300, VPI PS, etc).
24 V Power Supply.
8 cards per crate, 4 interlock per card: Up to 32 interlocks.
Optocoupling system between every interlock and the system.
Usage of basic electronic components and optocouplers.
Low delay
1 LED per controller: ON: OK
OFF: Interlock
Miguel Angel Quero Corrales

22. VVGS Interface crate and cards
Direct connection to the VVGS.
48 V Power Supply.
8 cards per crate: Up to 8 VVGS.
Optocoupling system between every VVGS and the system.
Usage of basic electronic components and optocouplers.
Low delay
Bi-color LED
GREEN: Open RED: Closed
LED
ON: Presence
OFF: No presence
Miguel Angel Quero Corrales

23. Preliminary test results. Temporal characterization
VVGS Interface crate
VVGS controller (SVCU)
Interlock Interface crate
Remote I/O crate
Interlock crate
Changes:
Slight decrease with more efficient code.
Slight increase with additional code to manage PROFINET and Master PLC communication.
Old system
(Interlock + SVCU)
New system (Interface + Remote I/O)
Total delay [ms]
199.8
6.5
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24. Cost estimations (per crate)
3,071 €
2,952 €
4,165 €
Miguel Angel Quero Corrales

25. Cost estimations (full system integration in point 5)
Proposed system: 2 Remote I/O + 5 Interlock Intf VVGS Intf. crates
Current system: 32 Interlock + 6 SVCU crates
Miguel Angel Quero Corrales

26. Miguel Angel Quero Corrales
3. Future work
Miguel Angel Quero Corrales

27. Miguel Angel Quero Corrales
Future work
Preliminary results
Performance tests.
Make common design for CPS, SPS, and LHC.
Further development on software for increased efficiency, lower latency and more safety.
Inclusion of PROFINET fieldbus for communication between Remote I/O crates and the Master PLC.
Development of SCADA application for HMI panels (enabling local control) integrated with current SCADA for remote control.
PROBLEMS
VVGS pinout
Number of VVGS to control
Ongoing
Miguel Angel Quero Corrales

28. Thank you for your attention
Miguel Angel Quero Corrales
TE-VSC-ICM
Vacuum, Surfaces & Coatings Group
Technology Department

29. And thank you all !!! Technology Department
Vacuum, Surfaces & Coatings Group
Technology Department

30. Characterization of TPG300 for test bench for PE 300T11 card
SMU (current source)
Focusing on the TPG 300 controller. Before beginning the test itself, it was required to know if the proposed test-bench in which the input generated by the Penning gauge was simulated by a SMU (sourcemeter unit)
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31. Cost estimations (full system)
Implementation cost of prototype at LHC
2 Remote I/O + 5 Interlock Intf. + 5 VVGS Intf.
Miguel Angel Quero Corrales