5. Synchronous memory modules

5. Synchronous memory modules
Dezső Sima September 2008 (Ver. 1.0)  Sima Dezső, 2008

Overview 1. Design space of memory modules 2. Basic features
3. Registering 4. ECC 5. Presence detect 6. Keying 7. Summing up the main features of memory modules 8. References

1. Design space of memory modules (1)
Layout of memory modules Layout of memory modules Basic features of memory modules Registering (Buffering) ECC Presence detect Keying Figure: Main dimensions of the design space of the layout of memory modules

2. Basic features (1) Basic features of memory modules Module type
Module width (Data/Data+ECC) No. of module sides populated No. of ranks provided on the module Figure: Basic features of memory modules

Figure : Main module types of general use
2. Basic features (2) Module types Memory card (build up of DIPs) Figure : Main module types of general use

2. Basic features (3) Memory cards
DRAMs packaged in DIPs1 mounted on a PC-card 2 attached via the ISA bus or a dedicated bus of the motherherboard used as the main memory or add-on memory in early PCs (8088 or based). 1 DIP: Dual In-line Package 2 PC: Printed Circuit

2. Basic features (4) Figure: 8-Bit ISA PC Memory Card (Gold 5150) [12]

2. Basic features (5) Module types Memory card SIPP (build up of DIPs)
(Single In-line Pin Package) Memory card (build up of DIPs) Figure : Main module types of general use

2. Basic features (6) 1 Byte wide 30 pins Figure: SIPP module [11]

2. Basic features (7) Module types (Single In-line Memory Module) SIMM
Memory card SIPP (build up of DIPs) (Single In-line Pin Package) Figure : Main module types of general use

2. Basic features (8) FPM 1-Byte/30-pin FPM/EDO 4-Byte/72-pin
Figure: SIMM modules

Figure : Main features of SIMM modules
2. Basic features (9) SIMM 30-pin 72-pin Width (Data/Data+parity) (8/9-bit) (32/36-bit) DRAM-type FPM FPM EDO First introduced in Intel’s chipsets (~1986?) 1993 1995 Voltage 5 V 5 V/3.3 V 5 V/3.3 V Typ. module capacity 256 KB – 8 MB 2 – 32 MB 4 – 64 MB Typ. use in connection with the processors 286 early 386 late 386 486 early Pentium 486 Pentium Figure : Main features of SIMM modules

2. Basic features (10) Module types Memory card SIPP SIMM DIMM
(built up of DIPs) (Single In-line Pin Package) (Single In-line Memory Module) (Dual In-line Memory Module) Figure : Main module types of general use

SDRAM 168-pin DDR 184-pin DDR2 240- pin DDR3 240-pin Figure: DIMM modules (8-Byte wide)

Figure : Main features of DIMMs
2. Basic features (12) DIMM 168-pin 240-pin 184-pin Width (Data/Data+ECC) DRAM-type EDO DDR2 DDR (64/72-bit) SDRAM FPM DDR3 Voltage 5 V/3.3 V 1.8 V 2.5 V 3.3 V 5 V/3.3V 1.5 V Typ. capacity [MB] 1-16 256–4096 128 –1024 16-512 512–496 Typ. use with the processors Pentium (3.3V) Pentium 4 Pentium D Core2 Duo Pentium (3.3V) Pentium II Pentium III DIMM first intro. in Intel’s chipsets (1996) (2004) (2002) (1995) (2007) Figure : Main features of DIMMs

2. Basic features (13) Module types SODIMM
(Small Outline Dual In-line Memory Module) Memory card SIPP SIMM DIMM (build up of DIPs) (Single In-line Pin Package) (Single In-line Memory Module) (Dual In-line Memory Module) Figure : Main module types of general use

2. Basic features (14) SDRAM 4 Byte/72 pin DDR2 8 Byte/200 pin
Figure: SO-DIMM modules

Figure : Main features of SODIMM modules
2. Basic features (15) SODIMM 72-pin 204-pin 144-pin Width (Data) EDO DDR2 DDR 32-bit 64-bit FPM DDR3 Voltage 5 V/3.3 V 1.8 V 2.5 V 3.3 V 5 V/3.3V 1.5 V Typ. capacity [MB] 4-64 256–2048 128 –1024 8-64 512–4096 Est. year of intro. ~1995 2004 2002 ~1996 ~1994 2007 SDRAM 64-512 1996 200-pin Figure : Main features of SODIMM modules

2. Basic features (16) Modules width (Data/Data+ECC)
1-byte wide modules 4-byte wide modules 8-byte wide modules (8/9-bits) (32/36-bits) (64/72-bits) 8088-based PCs (1981): byte wide data bus, 80286 based PCs (1984): 2-byte wide data bus 386 (1985) and 486 (1988) based PCs: 4-byte wide data bus Pentium (1993), and subsequent processors: 8-byte wide data bus Figure : Memory module widths vs data bus width of the processor bus in x86 processors

populated on both sides
2. Basic features (17) Number of memory module sides populated Memory module populated on one side Memory module populated on both sides Includes usually one rank Includes usually two ranks but may include also just one rank Figure: Population alternatives of memory modules

2. Basic features (18) Both alternatives are used by the manufacturers
Number of ranks provided on the memory module Single rank Two ranks Both alternatives are used by the manufacturers Figure: Number of ranks provided on the memory module

3. Registering (1) Registering Main memories of desktops/laptops
Unregistered modules Registered modules Main memories of desktops/laptops Main memories of servers Typical use With module type -- DIMM ECC Typically no Typically yes Figure: Registering alternatives of memory modules

3. Registering (2) Unregistered DIMMs (UDIMMs)
Typical use: in desktops/laptops (Memory capacities: up to a few GB) Registered DIMM (RDIMM) Typical use: in servers (Memory capacities: a few tens of GB) Problems arising while implementing higher memory capacities Higher memory capacities need more modules Higher loading the lines Signal integrity problems Buffering address and command lines, Phase locked clocking of the modules

3. Registering (3) Typical implementation
Two register chips, for buffering the address- and command lines A PLL (Phase locked loop) unit for deskewing clock distribution. ECC Register PLL Figure:Typical layout of a registered memory module with ECC [24]

3. Registering (4) S D R A M PI74SSTV168 57 Register Address/Control form Motherboard Address Control from Motherboard PI6CV857 PLL Input Clock for Motherboard Data From / To Motherboard Figure: Example. Block diagram of a registered DDR DIMM [29]

3. Registering (5) Register chips Aim
Buffering address and control lines, in order to increase the number of supported DIMM slots (max. mem. capacity) needed first of all in servers, by reducing signal loading in a memory channel. Number of register chips required Synchronous memory modules have about address and control lines, Register chips buffer usually 14 lines, Typically, two register chips are needed per memory module [29].

3. Registering (6) Functional block diagram
DQ DQM CS# U12 U4 U10 U13 U1 U14 U2 U11 R E G I S T PPL Functional block diagram of a registered SDRAM DIMM [28], with one rank, built up of 8 x8 SDRAMs 1 ECC unit 1 Register unit 1 PLL unit and 1 SPD unit.

3. Registering (7) Registering (buffering) the address and control lines R E G I S T REGE: Register enable signal Figure: Registered signals in case of an SDRAM memory module [28] Note: Data (DQ) and data strobe (DQS) signals are not registered.

3. Registering (8) PLL unit (Phase locked loop unit)
The need to deskew the clock signal distributed on the memory module Clock signals (CK) are sent in parallel with the address and control signals from the memory controller and need to be distributed to the DRAM devices and register units mounted on the module. Clock distribution means amplification and branching the clock signal typically up to 9-18 DRAM devices and 2 register units (one/two sided populated modules). The circuitry implementing clock distribution causes a skew between the input clock and the clock signals arriving at the DRAM and register chips. Clock skew reduces the width of the usable window and thus limits the operation speed. A PLL mounted to the memory module deskews the clock and thus improves timing budget and raises operating speed.

(actually in case of an SDRAM module) (based on [21])
3. Registering (9) Figure: The task of clock distribution in case of a double sided registered memory module (actually in case of an SDRAM module) (based on [21])

3. Registering (10) CK-1 CK-2 Skew Figure: Skew due to capacitive loading of the clock line (CK-2)

3. Registering (11) Center aligned clock Skewed clock
Available DVW Available DVW Data Data CK CK tS tS tH tH Min. DVW Min. DVW Figure: Reduction of operation tolerances due to clock skew (ideal signals assumed) A larger skew would even jeopardize or prevent correct operation Deskewing of clock distribution is needed

3. Registering (12) Principle of deskewing by means of a PLL (Phase Locked Loop) unit The signal to be deskewed VCO: Voltage Controlled Oscillator Operation The PLL unit compares the phases of the Ref. signal and the signal to be deskewed, generates an error signal and controls the VCO with this error signal. Figure: Principle of deskewing by means of a PLL (Based on [20])

3. Registering (13) PLL Figure: Typical clock distribution schemes of one- and two-sided SDRAM modules [28], [41], [21] Note: CK0 is an open ended signal

3. Registering (14) PLL Figure: Typical clock distribution schemes of two-sided DDR/DDR2 modules [13], [14] Note: CK0 is a differential signal

3. Registering (15) Note In case of SDRAM devices the clock signal is used to gate in the address, control and data lines, in case of DDR/DDR2/DDR3 devices the clock signal is used to gate in the address and control lines, whereas the data lines are gated in by the data strobe signals (DQS). Examples PLL on an SDRAM modules

3. Registering (16) Functional block diagram
DQ DQM CS# U12 U4 U10 U13 U1 U14 U2 U11 R E G I S T PPL SPD EEPROM A0 WP A1 A2 Functional block diagram of a registered SDRAM DIMM with one rank [28], built up of 8 x8 SDRAMs 1 ECC unit 1 Register unit and 1 PLL unit.

3. Registering (17) Functional block diagram of a registered DDR3 DIMM
DQ CMU CS# ZQ NW TRDQS DQS# DQS TRDQS# U15 U9 U14 U10 U13 U11 U12 U1 U21 U2 U20 U3 U19 U4 U18 U5 U17 Temperature senson/ SPD EEPROM A0 EVT A1 A2 DDR3 SDRAM R e g i s t r n a d P L Functional block diagram of a registered DDR3 DIMM with 2 ranks [15], built up of 16 x8 DDR3 devices 2 ECC unit 1 Register and PLL unit and 1 Temp. sensor/SPD unit.

3. Registering (18) R e g i s t r a n d P L Figure: Integrated register and PLL unit of a DDR3 DIMM [15]

3. Registering (19) Implementation of the clock distrubution circuitry including a PLL unit PLL IN OUT1 OUT ‘N’ Feedback SDRAM Stack Reg. 1 Reg. 2 Figure: Overview of a clock distribution circuitry intended for DDR devices [16]

3. Registering (20) The clock distribution circuitry including PLL became standardised by JEDEC in connection with DDR devices in 2000 [17] 10 outputs to the DDR devices and the register unit(s) Input of the feedback loop Phase lock between FBIN/FBOUT and CK Output of the feedback loop Figure: Block diagram of the clock distribution circuitry [17]

3. Registering (21) The operation of the PLL unit
The PLL unit compares the phases of the output clock signal (FBOUT) and the input clock signal (CK) and generates an error signal which is fed back to control the PLL unit in order to achieve a phase match between FBOUT/FBIN and the incoming clock signal (CK) as close as possible. The output of the PLL unit (Yi/Yi#) can be considered as the negatively delayed clock signal (CK).

3. Registering (22) Use of PLLs in main memories
In connection with the main memory PLLs are widely used to deskew signals or to align signal edges, such as SDRAM/DDR/DDR2/DDR3 modules include PLLs to deskew clock distribution on the memory card (as discussed above), DDR/DDR2/DDR3 SDRAM devices include PLLs to achieve a phase match of the Data Strobe Signal (DSQ) with the data signals (DQ) in case of data reads, DDR/DDR2/DDR3 SDRAM memory controllers use PLLs in case of data writes to center align write data (DQ) with the data strobe signal (DQS) and align the edges of DQS with CK, in case of data reads the device sends edge aligned data (DQ) with the DQS, it is the task of the controller’s PLL to shift DQS edge to the center of the data read. In multi module memory systems PLLs are utilized to deskew clocking.

3. Registering (23) Figure: Aligning read and write data in DDR/DDR2/DDR3 devices [19]

3. Registering (24) Remark If there are multiple DRAM modules connected to a memory channel an extra PLL is needed to deskew the multi-module memory system PLL or Clock Buffer Memory Controller or Bus Re-drive Chip 1 2 4 3 Figure: Deskewing a multi-module memory system by a PLL [29]

4. ECC (1) Module with ECC Figure:Registered memory card with ECC [24]

4. ECC (2) ECC basics (as used in SDRAMs)
Implemented as SEC-DED (Single Error Corretion Double Error Detection) Single Error Correction For D data bits P check-bits are taken. Data bits Check bits Figure: The code word The minimum number of check-bits (P) for single bit error corection ? Requirement: 2P ≥ the minimum number of states to be distinguished.

4. ECC (3) The minimum number of states to be distinguished:
D + P states to specify the bit position of a possible single bit error in the code word for both data and check bits, one additional state to specify the „no error” state. the minimum number of states to be distinguished is: D + P + 1 Accordingly: to implement single bit error correction the minimum number of check bits (P) needs to satisfy the requirement: 2P ≥ D + P + 1

4. ECC (4) Double error detection
an additional parity bit is needed to check for an additional error. Then the minimum number of check-bits (CB) needed for SEC-DED is: CB = P + 1 i.e. 2CB-1 ≥ D + CB 2CB-1 ≥ D + CB Data bits (D) Check bits (CB) 1 2 3:2 3 7:4 4 15:8 5 31:16 6 63:32 7 127:64 8 255:128 9 511:256 10 Table: The number of check-bits (CB) needed for D data bits

4. ECC (5) Principle of ECC coding
A constructor matrix [C] defines the check-bits [CB]: [CB] = [D] × [C] E.g. The constructor matrix [C] used in [22] is:

4. ECC (6) Table: The constructor matrix [C]
used in [22] to generate the check-bits [CB] (Modified Hamming code)

4. ECC (7) Calculation of the check-bits [CB] while using the constructor matrix [C] given before: [CB0] = [D1] [D2] [D3] [D5] [D8] [D9] etc. + + + + + [CB1] = [D0] [D1] [D2] [D4] [D6] [D8] etc. + + + + + . . . [CB7] = [D0] [D1] [D2] [D3] [D4] [D5] etc. + + + + + + denotes the EXCLUSIVE OR operation

4. ECC (8) Principle of error detection and correction [23]:
First a generator matrix [G] is constructed from the identity matrix [I] and the constructor matrix [C] as follows: [G] = [I, C] E.g. An 8 × 8 identity matrix [I] is: [I] =

4. ECC (9) Then the code word vector [D, CB] will be multiplied with the transpose of the generator matrix [G’]1, yielding the syndrome vector [S]: [S] = [D, CB] × [G’] E.g. for a code word consisting of 64 bit data and 8 check bits an 8 bit syndrom vector is calculated. Interpretation of the syndrome vector: if all elements of the syndrome vector are zeros, no error occured, else the syndrome vector [S] identifies the error type and location of any single bit errors. E.g. Interpretation of the syndrome vector [S] in [22]: 1 The transpose of the matrix [G] is the matrix [G’] where the lines of the matrix [G] become the rows of the matrix [G’].

4. ECC (10) Table: Interpretation of the bits of the syndrome vector [S] in [22] to identify possible errors

4. ECC (11) A single bit error is then corrected by reverting the erroreneous bit in the identified position, or a double or multiple bit error is reported. Implementation of SEC (in memories assuming 64-bit access width)

4. ECC (12) Figure: Block diagram of a 64-bit SEC-DED error correction/detection unit [22]

4. ECC (13) Operation (without taking use of the read/write FIFO buffers) Writing data to memory Incoming data (SD0-63) are simply forwarded through the latches and multiplexers to the memory (MD0-63). Checkbits are generated and also fowarded to the memory (CBSYN0-7) Reading data from memory Memory and checkbit data are latched in (MD0-63/CB0-7). Internal MD checkbits are generated and compared to the incoming checkbits. Syndrome bits are also generated and used to detect and correct errors. Finally, memory data (MD0-63) (corrected if needed and feasible) are forwarded to the memory controller. ECC operation increases memory latency by about ns (time delay between SDin 0-63 to MDout0-63 and vice versa).

5. Presence detect (1) Presence detect (PD)
After turning on the computer the BIOS1 runs the POST2 routine, that among others detects the presence and key features of the subsystems that make up the computer, such as the memory. Early memory modules (starting with SIMM/30 and in larger scale with SIMM/72) PPD (Parallel Presence Detect) Subsequent memory modules (starting with DIMM/168) SPD (Serial Presence Detect) 1 BIOS: Basic Input/Output System 2 POST: Power-On Self-Test

5. Presence detect (2) PPD Usually 4-8 pins of the edge connector of the module represent key features, such as memory density, organisation, speed etc. E.g. For a SIMM/72 module: Pin Use Interpretation 65 DQ15 Data 15 66 n/c Not connected 67 PD1 Presence Detect 1 68 PD2 Presence Detect 2 69 PD3 Presence Detect 3 70 PD4 Presence Detect 4 71 72 VSS Ground

5. Presence detect (3) Coding and interpretation of the present detect (PD) bits: PD bits are subdivided into subfields, each subfield is binary coded, binary code has a given interpretation. PD4 PD3 Access time 50, 100 ns 1 80 ns 70 ns 60 ns Implementation of the coding: 0: a resistor connects the pin to ground 1: no resistor As new DRAM technologies (such as FPM, EDO, SDRAM) introduce new features: more and more edge connector pins would be required.

5. Presence detect (4) SPD Based on
an 8-pin EEPROM (Erasable/Programmable Read-Only Memory) of 256-Byte, connected via a separate I2C bus to the memory controller. Figure: SPD chip on a DDR3 module [25] Figure: 8 pin-SPD EEPROM [26]

5. Presence detect (5) Relevant features of the memory modules are held in a byte organised table, called the SPD table. The SPD table is standardized by JEDEC (1997) Each byte reflects a particular feature and has a numeric (decimal/hexadecimal) value. E.g. Table: Excerpt of an SDRAM SPD table [27]

5. Presence detect (6) Basic table format Bytes 0 –127: allocated
: free for the user (except DDR3 SPD tables, where bytes 0 – 175 are allocated). Coding of the table entries (bytes) is given in the appropriate JEDEC Module Serial Presence Detect Specification. E.g. Coding of bytes 3 and 4 of DDR3 SPD tables:

5. Presence detect (7) Byte 3 Module type 00H Undefined
01H Registered DIMM (RDIMM) 02H Unregistered DIMM (UDIMM) 03H Small Outline DIMM (SODIMM) Byte Device density 01H Mb 02H Gb 03H Gb 04H Gb The SPD may also contains manufacturer's data, such manufacturer’s ID, part number, etc.

5. Presence detect (8) As DRAM technology evolves
the SPD table needs to hold more and more DRAM features. Different SPD table formats for different DRAM technologies (FPM/EDO, SDRAM, DDR, DDR2, DDR3) SPD table formats for (FPM/EDO, SDRAM, DDR, DDR2, DDR3) modules differ significantly.

5. Presence detect (9) Table: Sample SPD table for FPM/EDO modules [27]

5. Presence detect (10) Table: Sample SPD table for SDRAM
modules (1) [27]

5. Presence detect (11) Table: Sample SPD table for SDRAM modules (2) [27]

5. Presence detect (12) Table: Sample SPD table for DDR3
modules (1) [25]

5. Presence detect (13) Table: Sample SPD table for DDR3
modules (2) [25]

5. Presence detect (14) I2C bus (Inter-IC bus)
Low-speed serial bus, using a serial bidirectional clock line (SCL) and a serial bidirectional data line (SDA). After powering up the computer, the memory controller reads the content of the SPD table during running the POST routine through this serial bus.

6. Keying (1) Keying the modules
From the SIMM 72 on both memory modules and sockets have keys (notches) to prevent inserting not fitting modules into the sockets. Example: Keys Figure: Module keys on an SDRAM DIMM [1] The keys may indicate supply voltage (5 V/ 3.3 V), module type (like RIMM etc) or presence of SPD. The position and interpretation of the keys is standardised by JEDEC, (in the standards MO-116 for SIMM 72 modules, MO-161 for SDRAM DIMMs etc.)

6. Keying (2) Examples 72-pin FPM/EDO SIMMs
Figure: Keying of 72-pin SIMMs (FPM or EDO DRAMs) [2]

6. Keying (3) 168-pin SDRAM DIMMs
Figure: Keying of 168-pin SDRAM DIMMs [3]

6. Keying (4) 184-pin DIMMs DDR [4] RIMM [5]
Figure: Keying of 184-pin DIMMs

6. Keying (5) Figure: 184-pin RIMM module (Rambus DRAM) [18]

6. Keying (6) 240-pin DIMMs DDR2 [6] DDR3 [7] FB-DIMM [8]
Figure: Keying of 240-pin DIMMs

6. Keying (7) Figure: Keying diferences of DDR and DDR2 modules [9]

6. Keying (8) Figure: Keying differences of DDR3 (top) and DDR2 (bottom) modules [10]

7. Summing up the main features of memory modules (1)
SIMM 30-pin 72-pin Width (Data/Data+parity) (8/9-bit) (32/36-bit) DRAM-type FPM FPM EDO First introduced in Intel’s chipsets (~1986?) 1993 1995 Voltage 5 V 5 V/3.3 V 5 V/3.3 V Present detect On a few implementations PPD (4-bit) PPD (4-bit) Unreg./registered unregistered unregistered unregistered Typ. module capacity 256 KB – 8 MB 2 – 32 MB 4 – 64 MB Typ. use in connection with the processors 286 early 386 late 386 486 early Pentium 486 Pentium Figure : Main features of SIMM modules

DIMM 168-pin 184-pin 240-pin Width (Data/Data+ECC) (64/72-bit) (64/72-bit) (64/72-bit) DRAM-type FPM EDO SDRAM DDR DDR2 DDR3 DIMM first intro. in Intel’s chipsets (1995) (1996) (1996) (2002) (2004) (2007) Voltage 5 V/3.3V 5 V/3.3 V 3.3 V 2.5 V 1.8 V 1.5 V Present detect PPD (8b PPD (8b) SPD (opt) SPD SDP SPD SPD Unreg./registered both both both both both unreg. (yet) Typ. capacity [MB] 1-16 1-16 16-512 128 –1024 256–4096 512–496 Typ. use with the processors Pentium (3.3V) Pentium (3.3V) Pentium (3.3V) Pentium II Pentium III Pentium 4 Pentium 4 Pentium D Core2 Duo Core2 Duo Figure : Main features of DIMMs

SODIMM 72-pin 144-pin 200-pin 204-pin Width (Data) 32-bit 64-bit 64-bit 64-bit FPM EDO EDO SDRAM DDR DDR2 DDR3 Est. year of intro. ~1994 ~1995 ~1996 1996 2002 2004 2007 Present detect PPD (7b) PPD (7b) SPD SPD SDP SPD SPD Registered option No No No No No No No Typ. capacity [MB] 4-64 4-64 8-64 64-512 128 –1024 256–2048 512–4096 Voltage 5 V/3.3V 5 V/3.3 V 3.3 V 3.3 V 2.5 V 1.8 V 1.5 V Figure : Main features of SODIMM modules

5. References (1) [1]: 64MB Apple G3 Beige 168p SDRAM DIMM, [2]: 4, 8 MEG x 32 DRAM SIMMs, Micron, [3]: 168 Pin, PC133 SDRAM Registered DIMM Design Specification, JEDEC Standard No. 21-C, Page [4]: 184 Pin Unbuffered DDR SDRAM DIMM Family, JEDEC Standard No. 21-C, Page [5]: Direct Rambus DRAMM RIMM Module, 512 MB, MC-4R512FKE6D, Elpida, [6]: DDR2 SDRAM UDIMM Features, Micron, [7]: DDR3 SDRAM UDIMM Features, Micron, [8]: DDR2 SDRAM FBDIMM Features, Micron, [9]: Torres G., „Memory Tutorial”, July 19, 2005, Hardwaresecrets, [10]: Besedin D., „First look at DDR3”, Digit-life, June 29, 2007,

5. References (2) [11]: [12]: W0QQitemZ QQcmdZViewItem [13]: Datasheet, Micron, DDF18C64_128x72D.pdf [14]: Datasheet, Micron, HTF18C64_128_256x72D.pdf [15]: Datasheet, Micron, JSF18C256x72PD.pdf [16]: Supermicro Motherboards, [17]: Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications, JESD82, JEDEC, July 2000 [18]: [19]: Haskill, „The Love/Hate relationship with DDR SDRAM Controllers,” Mosaid, Oct. 2006, SDRAM_Controller_whitepaper_Oct_2006.pdf [20]: Van Roon T., „What exactly is a PLL?,” April 2006, [21]: Interfacing to DDR SDRAM with CoolRunner-II CPLDs, Application Note XAPP384, Febr. 2003, XILINC inc.

5. References (5) [22]: 64-bit Flow-Thru Error Detection and Correction Unit, IDT49C466, Integrated Device Technology Inc., 1999, datasheet/222/IDT49C466.php [23]: Tam S., „Single Error Correction and Double Error Detection,”, XILINX Application Note XAP645 (v.2.2), Aug. 2006, application_notes/xapp645.pdf [24]: DDR SDRAM Registered DIMM Design Specification, JEDEC Standard No. 21-C, Page , Jan. 2002, [25]: Understanding DDR3 Serial Presence Detect (SPD) Table, July 17, 2007, Simmtester, [26]: DDR2 DIMM SPD Definition, August 25, 2006, [27]: Memory Module Serial Presence-Detect, TN-04-42, Micron, 2002 [28]: Datasheet, SD9C16_32x72.pdf [29]: Solanki V., „Design Guide Lines for Registered DDR DIMM Module,” Application Note AN37, Pericom, Nov. 2001,

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