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Piero Belforte, HDT High Design Technology presentation by Alessandro Arnulfo (1999).

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Presentation on theme: " Piero Belforte, HDT High Design Technology presentation by Alessandro Arnulfo (1999)."— Presentation transcript:

1 1 HDT Italia s.r.l. High Design Technology Headquarters TORINO (ITALY) Corso Trapani, 16 Tel. +390.11.746104 Fax. +390.11.748109 Alessandro Arnulfo R&D Application Engineer

2 2 HDT Italia s.r.l. Founded in 1990 with the aim to develop and market high- performance EDA tools Focused on: –Signal Integrity (SI) –Hardware modelling –Design&Validation of digital systems –EMC/EMI issues

3 3 Consulting & Services on : –Signal Integrity and EMC/EMI evaluation ( from PCB to the whole system ) –Modeling –Specific customer needs –Definition of design&qualification methodologies –Test & Measurement –Software customization HDT Italia s.r.l.

4 4 HDT Italia s.r.l PRODUCTS PRESTO ( Post-layout Rapid Exhaustive Simulation and Test of Operation)

5 5 HDT Italia s.r.l PRODUCTS SPRINT ( Simulation Program of Response of Integrated Network Transients) SIGHTS ( Standard Interface for Graphic Handling of Transient Signals )

6 6 EmiR ( Emission Radiated) TEMA ( Transverse ElectroMagnetic Analysis) HDT Italia s.r.l PRODUCTS

7 7 PRESTO Post-layout Rapid Exhaustive Simulation and Test of Operation

8 8 Application Domain Signal Integrity investigation –efficient handling of huge number of transmission lines –simultaneous analysis of transmission, crosstalk and switching noise issues High-speed and complex system design&validation MCM, PCB, Backplane, Interconnection layout check EMC/EMI analysis Hardware quality verification

9 9 Application Market Telecom Computer Automotive Aerospace Automatic Test Equipment Measurement Biomedical Consumer Electronics

10 10 Technologies supported PCB MCM Hybrid Interconnect levels multiboards backplane LANS entire apparatus

11 11 Platforms supported HP 9000/700 Series Sun SPARC Series Windows NT 4.0 (Intel)

12 12 PRESTO Structure PREFIS SPRINT Output FLOWMANAGERFLOWMANAGER FLOWMANAGERFLOWMANAGER Model Capture System PRLib S.I. report SIGHTS CadExtract CAD DATA BASE

13 13 PRESTO CadExtract Links to –Mentor Graphics, Boardstation –COOPER&CHYAN TECHNOLOGY, SPECCTRA –Cadence, Allegro –Zuken Redac, Visula –INCASES, THEDA –Accel, P-CAD Complete data extraction of –physical layout –electrical data

14 14 Powerful simulation engine (SPRINT) Concurrent simulation of entire systems or selected nets Exhaustive checks of complex PCB in minutes Validated for high-speed applications up to 1Gbit/s Signal Integrity investigation –Crosstalk Analysis –Simultaneous Switching Noise PRESTO Features

15 15 PRESTO Features (cont’d) Automated compliance analysis –mask&wide range of stimulus patterns –enhanced test capabilities User definable enhanced Signal Integrity analysis and report Time Domain Reflectometry based modeling and simulation Link to measurement equipment Link to analog simulators

16 16 PRESTO Features (cont’d) Flexible model topologies&management –Automatic package assignment –Multipower pin management What-if analysis of packages and components Distributed models of ground and power nets including planes Multi level modeling and simulation –electrical –timing –logic –system

17 17 PRESTO Results

18 18 PRESTO Board layout to PRESTO

19 19 SPRINT Simulation Program of Response Integrated Network Transients Uses DSP-based algorithm –simulation time increases linearly with complexity –uses fixed time step –no convergence problems Very fast to handle large systems Efficiently handles inductors&transmission lines Uses accurate, efficient behavioural models for drivers and receivers

20 20 COMPARISON SIMULATION&MEASUREMENT Comparison between simulation and measures of high-speed multiboard system (155Mbit/s) * 50000 elements * 32 simultaneous input sequence * 16000 time points * 60 min. simulation time (HP 750)

21 21 PRESTO FOR EMC I) Susceptibility Conducted Noise Susceptibility (CNS) # modelling capabilities EMC models # noise injection and propagation # What- if analysis: - filtering analysis (schematic) - layout traces analysis (topology) EMC project in Automotive field on a 2-layers analog / digital board good comparisons with measurements

22 22 PRESTO FOR EMC Susceptibility to direct perturbations (not already automatically inserted) # plane-wave model # electrical equivalent models to simulate the perturbation effects on the PCB nets

23 23 PRESTO FOR EMC II) Emissions Conducted Emissions (CE) # modelling capabilities EMC models # What- if analysis # visualize the Conducted Emissions spectrum in the input stage of the board EMC project in Aerospace field on a multi-layered analog board good comparisons with measurement

24 24 PRESTO FOR EMC Radiated Emissions (RE): EMIR (EMIssions Radiated) Prediction of PCB radiated ElectroMagnetic Interference (EMI) at the design state

25 25 EMIR Display of PCB net radiation spectrum at user selected distances to compare with EMC normative. Uses Green Dyadic functions of actual PCB medium Takes into account the board cross-section in the EM Field calculation.

26 26 EMIR Interfaced with PRESTO, it uses accurate differential mode current distribution given by SPRINT simulator Effects like reflections, impedance mismatches, ground-bounce, actual VCC/GND planes influence can be taken into account simultaneously. Predicts VCC/GND nets radiation

27 27 EMIR Display of PCB radiation diagrams at user selected frequencies for Localization of EMI problems Near-field algorithm for H field Takes into account the measurement setup: –antenna polarization –metal floor of semi-anechoic chamber

28 28 EmiR_Cable Radiation due to common mode current that spreads along cables: - PCB which ground plane is connected to a cable. - shielded coaxial cable - twisted cable Use of fast 3D algorithm based on PEEC method

29 29 MODELLING OF PARASITIC COUPLINGS

30 30 Parasitic parameters evaluation: PEEC (Partial Elements Equivalent Circuit) l Numerical method for the circuital modelling of parasitic effects in 3D structures of conductors and dielectrics ; l Leads to an equivalent circuit reduction of the structure; l The equivalent circuit is formed only by lumped passive elements (RLC circuit);

31 31 PEEC METHOD l The structure is subdivided into parts: - conductive volume cells, where conduction current flows; - dielectric volume cells, where polarization current flows; - dielectric/dielectric or metal/dielectric surface cells, where electric charges are stored. l At each cell a different circuit element ( L, M, C, R) is associated (partial elements) l Using retarded controlled generator (retarded PEEC) it is possible to take into account the propagation delay of the signals

32 32 PEEC METHOD: EXAMPLE OF SUBDIVISION OF THE STRUCTURE IN SURFACE CELLS MACROMODEL APPROACH: a partial capacitance between each pair of cells is obtained; they are grouped leading to a mutual capacitance between each pair of conductors

33 33 PEEC METHOD: OPTIMIZATION l The number of cells used for the discretization is very important to obtain accurate results: it must be optimized; more accurate results possible numerical errors longer computation times l Good trade-off: uniform discretization; More cells

34 34 EMISSIONS OF THE PCB WITH AN ATTACHED CABLE Thevenin-like approach for the cable excitation: (PEEC) Inductive and Capacitive coupling Equivalent noise voltage generator controlled by voltage and current on the track (coefficients depending on PEEC parameters)

35 35 EMISSIONS OF THE PCB WITH AN ATTACHED CABLE l The Transmission Line Theory (TLT) to calculate the current distribution on the cable, modeled as a lossy transmission line l The Hertzian Radiating Dipoles Method to calculate the RE of the cable l The image principle to take into account the floor of the semi- anechoic chamber

36 36 l RE from one cable placed horizontally above the floor of the semi-anechoic chamber; l An inductive common mode filter (choke) placed in series to the cable; l A one-layer PCB (microstrip structure) horizontally or vertically oriented; l An unlimited number of tracks placed in any positions: optimized algorithm to avoid too long computation times due to PEEC matrices inversions; EMISSIONS OF THE PCB WITH AN ATTACHED CABLE (cont’d)

37 37 DESCRIPTION OF THE BOARD

38 38 DESCRIPTION OF THE SETUP 1 m 3 m 1,3 m 1,2 m cable diameter = 5mm shielded oscillator

39 39 COMPARISON BETWEEN MEASURED AND SIMULATED COMMON MODE CURRENT

40 40 COMMON MODE CURRENT THROUGH THE CABLE (EmiR_Cable)

41 41 COMPARISON BETWEEN THE MEASURED AND THE SIMULATED RADIATED FIELD

42 42 EMISSIONS OF THE PCB WITH AN ATTACHED CABLE (EmiR_CABLE) |E| [dB  V/m] Frequency in GHz

43 43 CONCLUSIONS ON SPRINT SPEED ENHANCES AND ABSENCE OF CONVERGENCE PROBLEMS ARE OBTAINED BY THE DWN APPROACH SIMULATION TIME RISES PROPORTIONALY WITH NETWORK COMPLEXITY LARGE NETWORKS CAN BE SIMULATED MIXED-MODE (ELECTRICAL/TIMING/LOGIC) SIMULATION IS SUPPORTED BTM MODELS EXTRACTED FROM TDR MEASUREMENTS ARE SUPPORTED HIGH SPEED DIGITAL SYSTEMS CAN BE SIMULATED

44 44 CONCLUSIONS ON MODELING SPRINT SYNTAX IS OPEN TO IBIS STANDARD 4-PORTS MODELS FOR I/O TAKE INTO ACCOUNT THE EFFECTS OF SUPPLY DISTRIBUTION NETWORK CAPABILITY TO MODEL ANALOG DEVICES FOR EMC SIMULATIONS CAPABILITY TO BUILD VERY ACCURATE MODELS (S PARAMETERS BASED) FOR HIGH SPEED DIGITAL SYSTEMS

45 45 CONCLUSIONS ON PRESTO FOR SI SPEED OF THE SIMULATION HIGH ACCURACY OF RESULTS, GOOD AGREEMENT WITH MEASUREMENTS SIMULTANEOUS SIMULATION OF ALL NETS OF A COMPLEX PCB IS AVAILABLE PRESTO CAN SIMULATE SIGNAL INTEGRITY, CROSSTALK BUT ALSO SIMULTANEOUS SWITCHING NOISE ON VCC/GND NETS OR PLANES PRESTO OFFERS FACILITIES LIKE EYE- DIAGRAMS TO STUDY HIGH-SPEED PCBS

46 46 CONCLUSIONS ON PRESTO FOR EMC PRESTO IS ABLE TO PREDICT RESULTS OF COMPLIANCE TESTS FOR: –RADIATED EMISSIONS –CONDUCTED NOISE SUSCEPTIBILITY –CONDUCTED EMISSIONS COMPARISONS BETWEEN SIMULATIONS AND MEASUREMENTS IN THE CONDITIONS REQUIRED BY EMC STANDARDS-> GOOD AGREEMENT

47 47 FUTURE EVOLUTIONS PORTING OF PRESTO ON WINDOWS-NT CUSTOM SOLUTIONS OTHER FEATURES FOR THE PREDICTION OF RADIATED EMISSIONS

48 48 APPLICATION OF HDT TECHNOLOGY/PRODUCTS WITHIN ZUKEN-REDAC ENVIRONMENT USE OF SPRINT AND TEMA (AND EmiR) TO DRIVE CONSTRAINTS TO BE APPLIED TO ZUKEN-REDAC ROUTER USE OF SPRINT, LIBRARIES AND SIGHTS TO PRODUCE ON-LINE SIMULATIONS


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