1. Chapter 2 Computer Evolution and Performance

2. ENIAC - background ENIAC(Electronic Numerical Integrator And Computer) was world’s first general purpose computer Designed & constructed by Eckert and Mauchly at University of Pennsylvania During WWII, The Army’s Ballistics Research Laboratory(BRL), wanted to make range and trajectory tables for artillery and new weapons The project was started 1943 and finished 1946 —Too late to be used in war effort It was used until 1955

3. ENIAC - details ENIAC was decimal machine (not binary)machine Its memory consisted of 20 accumulators, each capable of holding 10 digit-decimal number (totally processes 20 X 10 digit decimal numbers at the same time) It was programmed manually by switches (extremely tedious) Features of the ENIAC machine —18,000 vacuum tubes —30 tons —15,000 square feet —140 kW power consumption —5,000 additions per second

4. von Neumann/Turing The difficulty of the programming process of the ENIAC can be facilitated if the program could be represented in a form suitable for storing in memory The stored program concept was proposed by John von Neumann & Alan Turing, separately —Main memory storing programs and data —The idea is published in a 1945 proposal by von Neumann for a new computer, the EDVAC(Electronic Discrete Variable Computer) In 1946, von Neumann began the design of a new stored program computer (referred to as the IAS computer) —A main memory, which stores both data & instructions —An ALU capable of operating on binary data —A control unit interpreting instructions from memory and executing —Input and output equipment operated by control unit Completed 1952

5. Structure of von Neumann machine

6. IAS - details The memory of the IAS consists of 1,000 storage, called words, each has 40 bits size —Total memory size is 1,000 x 40 bit words —Number is represented by binary number —A word may also contain two 20-bit instructions

7. IAS - details Register set of IAS (storage in CPU) —Memory Buffer Register(MBR) : contains a word to be stored in memory or is used to receive a word from memory —Memory Address Register(MAR) : specifies the address in memory of the word to be written from or read into the MBR —Instruction Register (IR) : contains the 80bit opcode instruction being executed —Instruction Buffer Register (IBR): employed to hold temporarily the right hand instruction from a word in memory —Program Counter (PC) : contains the address of the next instruction-pair to be fetched from memory —Accumulator (AC), Multiplier Quotient (MQ) : employed to hold temporarily operands & results of ALU operations. For example, the result of multiplying two 40-bit numbers is 80- bit number: the most significant 40 bits are stored in the AC and the least significant in the MQ.

8. Structure of IAS – detail

9. Commercial Computers The 1950s saw the birth of the computer industry with two companies, Sperry and IBM In 1947, Eckert-Mauchly Computer Corporation was founded. Their first successful machine was UNIVAC I (Universal Automatic Computer) —which was commissioned by the US Bureau of Census 1950 calculations — intended for both scientific and commercial applications (matrix algebraic computations, statistical problems, etc.) Became part of Sperry-Rand Corporation In late 1950s - UNIVAC II was developed —Higher performance —More memory

10. IBM The punched-card processing equipment manufacturer started to deliver its first electronic stored-program computers (701, 702, etc.) In 1953 - the 701 —IBM’s first stored program computer —Intended for scientific calculations In 1955 - the 702 —Which had a number of hardware features that suited it to the business applications — It lead to 700/7000 series that established IBM as the dominant computer manufacturer

11. The Second Generation : Transistors The first major change in the electronic computer came with the replacement of the vacuum tube by the transistor The transistor is —Smaller —Cheaper —Less heat dissipation than a vacuum tube The vacuum tube requires wire, metal plates, a glass capsule, and a vacuum But the transistor is a solid state device, made from silicon (the sand!) The transistor was invented at Bell Labs in 1947 In late 1950s, the fully transistorized computers were commercially available

12. Transistor Based Computers Second generation machines —The use of the transistor —Also, the second generation machines have another changes – introduction of more complex arithmetic and logic units and control units – the use of high level programming languages NCR & RCA produced small transistor machines IBM 7000 DEC (founded 1957) —Produced PDP-1

13. Generations of Computer Vacuum tube - 1946-1957 Transistor - 1958-1964 Small scale integration - 1965 on —Up to 100 devices on a chip Medium scale integration - to 1971 —100-3,000 devices on a chip Large scale integration - 1971-1977 —3,000 - 100,000 devices on a chip Very large scale integration - 1978 -1991 —100,000 - 100,000,000 devices on a chip Ultra large scale integration – 1991 - —Over 100,000,000 devices on a chip

14. Moore’s Law Increased density of components on chip Gordon Moore – co-founder of Intel Number of transistors on a chip will double every year ( ~ Hwang’s law) Since 1970’s development has slowed a little —Number of transistors doubles every 18 months

15. Moore’s Law The consequences of Moore’s law are profound ! —The cost of a chip has remained virtually unchanged during this period of rapid growth in density —Because logic & memory elements are placed closer together on more density packed chips, the electrical path length is shortened, increasing operating speed —The computer becomes smaller, making it more convenient to place in a variety of environments —There is a reduction in power & cooling requirements —The interconnections on the IC are much more reliable than solder connections. With more circuitry on each chip, there are fewer inter-chip connections

16. Growth in CPU Transistor Count (Moore’s Law)

17. IBM 360 series In 1964, IBM announced the System/360 Replaced (& not compatible with) 7000 series First planned “family” of computers —Similar or identical instruction sets —Similar or identical O/S —Increasing speed —Increasing number of I/O ports (i.e. more terminals) —Increased memory size —Increased cost Multiplexed switch structure The System/360 had a profound impact on the entire industry. Many of its features become standard on other large computers

18. DEC PDP-8 Also in 1964, DEC(Digital Equipment Corporation) has announced the First minicomputer Did not need air conditioned room Small enough to sit on a lab bench $16,000 —IBM 360 is over $100k Embedded applications & OEM —The low cost and small size of the PDP-8 enabled another manufacturer to purchase a PDP-8 and integrate it into its own system BUS STRUCTURE

19. DEC - PDP-8 Bus Structure BUS structure : Omnibus -Consists of 96 separate signal paths, used to carry control, address, and data signals -Because all system components share a common set of signal paths, their use must be controlled by the CPU -This architecture is highly flexible, allowing modules to be plugged into the bus to create various configurations

20. Semiconductor Memory 1970 Fairchild Size of a single core —i.e. 1 bit of magnetic core storage Holds 256 bits Non-destructive read Much faster than core Capacity approximately doubles each year

21. Intel In 1971, 4004 —First microprocessor —All CPU components on a single chip —4 bit —Designed for specific applications Followed in 1972 by 8008 —8 bit —Designed for specific applications In 1974, 8080 —Intel’s first general purpose microprocessor

22. Designing for High Performance Pipelining On board cache On board L1 & L2 cache Branch prediction Data flow analysis Speculative execution

23. Performance Balance Processor speed increased Memory capacity increased Memory speed lags behind processor speed

24. Logic and Memory Performance Gap

25. Solutions Increase number of bits retrieved at one time —Make DRAM “wider” rather than “deeper” Change DRAM interface —Cache Reduce frequency of memory access —More complex cache and cache on chip Increase interconnection bandwidth —High speed buses —Hierarchy of buses

26. I/O Devices Peripherals with intensive I/O demands Large data throughput demands Processors can handle this Problem moving data Solutions: —Caching —Buffering —Higher-speed interconnection buses —More elaborate bus structures —Multiple-processor configurations

27. Typical I/O Device Data Rates

28. Key is Balance Processor components Main memory I/O devices Interconnection structures

29. Improvements in Chip Organization and Architecture Increase hardware speed of processor —Fundamentally due to shrinking logic gate size –More gates, packed more tightly, increasing clock rate –Propagation time for signals reduced Increase size and speed of caches —Dedicating part of processor chip –Cache access times drop significantly Change processor organization and architecture —Increase effective speed of execution —Parallelism

30. Problems with Clock Speed and Logic Density Power —Power density increases with density of logic and clock speed —Dissipating heat RC delay —Speed at which electrons flow limited by resistance and capacitance of metal wires connecting them —Delay increases as RC product increases —Wire interconnects thinner, increasing resistance —Wires closer together, increasing capacitance Memory latency —Memory speeds lag processor speeds Solution: —More emphasis on organizational and architectural approaches

31. Intel Microprocessor Performance

32. Increased Cache Capacity Typically two or three levels of cache between processor and main memory Chip density increased —More cache memory on chip –Faster cache access Pentium chip devoted about 10% of chip area to cache Pentium 4 devotes about 50%

33. More Complex Execution Logic Enable parallel execution of instructions Pipeline works like assembly line —Different stages of execution of different instructions at same time along pipeline Superscalar allows multiple pipelines within single processor —Instructions that do not depend on one another can be executed in parallel

34. Diminishing Returns Internal organization of processors complex —Can get a great deal of parallelism —Further significant increases likely to be relatively modest Benefits from cache are reaching limit Increasing clock rate runs into power dissipation problem —Some fundamental physical limits are being reached

35. New Approach – Multiple Cores Multiple processors on single chip —Large shared cache Within a processor, increase in performance proportional to square root of increase in complexity If software can use multiple processors, doubling number of processors almost doubles performance So, use two simpler processors on the chip rather than one more complex processor With two processors, larger caches are justified —Power consumption of memory logic less than processing logic Example: IBM POWER4 —Two cores based on PowerPC

36. POWER4 Chip Organization

37. Pentium Evolution (1) 8080 —first general purpose microprocessor —8 bit data path —Used in first personal computer – Altair 8086 —much more powerful —16 bit —instruction cache, prefetch few instructions —8088 (8 bit external bus) used in first IBM PC 80286 —16 Mbyte memory addressable —up from 1Mb 80386 —32 bit —Support for multitasking

38. Pentium Evolution (2) 80486 —sophisticated powerful cache and instruction pipelining —built in maths co-processor Pentium —Superscalar —Multiple instructions executed in parallel Pentium Pro —Increased superscalar organization —Aggressive register renaming —branch prediction —data flow analysis —speculative execution

39. Pentium Evolution (3) Pentium II —MMX technology —graphics, video & audio processing Pentium III —Additional floating point instructions for 3D graphics Pentium 4 —Note Arabic rather than Roman numerals —Further floating point and multimedia enhancements Itanium —64 bit —see chapter 15 Itanium 2 —Hardware enhancements to increase speed See Intel web pages for detailed information on processors

40. PowerPC 1975, 801 minicomputer project (IBM) RISC Berkeley RISC I processor 1986, IBM commercial RISC workstation product, RT PC. —Not commercial success —Many rivals with comparable or better performance 1990, IBM RISC System/6000 —RISC-like superscalar machine —POWER architecture IBM alliance with Motorola (68000 microprocessors), and Apple, (used 68000 in Macintosh) Result is PowerPC architecture —Derived from the POWER architecture —Superscalar RISC —Apple Macintosh —Embedded chip applications

41. PowerPC Family (1) 601: —Quickly to market. 32-bit machine 603: —Low-end desktop and portable —32-bit —Comparable performance with 601 —Lower cost and more efficient implementation 604: —Desktop and low-end servers —32-bit machine —Much more advanced superscalar design —Greater performance 620: —High-end servers —64-bit architecture

42. PowerPC Family (2) 740/750: —Also known as G3 —Two levels of cache on chip G4: —Increases parallelism and internal speed G5: —Improvements in parallelism and internal speed —64-bit organization

43. Internet Resources http://www.intel.com/ —Search for the Intel Museum http://www.ibm.com http://www.dec.com Charles Babbage Institute PowerPC Intel Developer Home