1. CSCM Test description and Risk assessment  Goal  The typical and ultimate current cycle  Test sequence for type test and regular test  Risk assessment  Strategy & planning for CSCM tests during LS1  Conclusion Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Arjan Verweij, on behalf of the CSCM team

2. CSCM main goal: qualification of the bus & bypass of the main circuits (RB, RQD/F) up to nominal current (7 TeV equivalent) at 20 K. Goal of the test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 The bus & bypass comprises: Current leads + Pigtails + Busbars + Diode leads + Diodes + all soldered/welded/brazed/bolted connections in-between.

3. The CSCM can qualify all these components in a few current cycles, and can also detect high resistive parts/contacts, which can then be repaired or monitored in time. Average numbers for each circuitRBRQ Nr of current leads per circuit42 Nr of connections between lead and pigtail42 Nr of connections between pigtail and busbar42 Nr of busbar joints420 Nr of T-connections30898 Nr of diode leads30898 Nr of ‘half moon’ connections308- Nr of connections between bus and connection plate-196 Nr of connections between bus and heat sink30898 Nr of connections between heat sink and diode30898 Nr of diodes15449 Goal of the test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Nr of circuits: 8 x RB, 8 x RQD, 8 x RQF

4.  Qualification should correspond in terms of heat deposition to an exponential decay from 12 kA with  =100 s (RB) or  =30 s (RQ) *.  Qualification should go to similar currents as the LHC because some contact resistances seem strongly current dependent. Current (kA)  (s) MIIt’s (10 6 A 2 s)Q diode (kJ) RB8.4682400600 1210072001260 1310084501365 RQ8.415530132 1230 * 2160378 1330 * 2535410 Goal of the test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 although we might be able to use  =15-22 s for the RQ circuits, I will assume  =30 s as the most conservative value.

5. Simulations have been performed to see what type of current cycle (plateau, linear ramp down, exp. ramp down, …) would be optimum to reach the required current and MIIt’s, taking into account constraints from the power converter and QPS. Simulation parameters: T He =20 K RRR bus =200 V diode =2.2 V @ 20 K, 1 V @ 60 K or above (To be checked in SM18) With & without cooling to GHe R diode-lead =10  (RB)-15  (RQ) L RB =L RQ =3.5 mH (so stored energy is 250 kJ at 12 kA) Goal of the test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

6. Typical current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

7. 1)Increase voltage of the converter with 20 V/s up to 500 A 2)Plateau of 10 s 3)Increase the current linearly from 500 A to I test in 12 s 4)Plateau of 2-100 s 5)Ramp the current exponentially down to 1000 A 6)Ramp the current linearly down to 0 A 1 2 3 4 5 6 Typical current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

8. Step 1: Ramp up to 500 A with 20 V/s to open all the diodes.  This step is scheduled to take 20 s.  The dipole diodes will start to conduct at about 50 A (using RRR=150, R MB,20K = 42 m  ).  The quad diodes will start to conduct at about 365 A (using RRR=150, R MQ,20K = 6 m  ).  During the rest of the measurement run, the current in dipoles and quads will be about 24 A and 165 A respectively, resulting in a power of 24 W and 165 W. Typical current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 1

9. Step 2: Check if the diodes are open and prepare for ramp  This step is scheduled to take 10 s. Step 3: Ramp up to test current with up to 1000 A/s  This step is scheduled to take 12 s.  Typical maximum inductive voltages during this step are: - 30 m dipole segment: U ind =20  H x 1000 A/s = 20 mV - 100 m quad segment: U ind =60  H x 1000 A/s = 60 mV Typical current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 2 3

10. Step 4: Plateau at the test current  Depending on the test, this step is scheduled to take between 2 and 100 s. Step 5: Ramp down to 1000 A  The ramp down is exponential, with time constants of about 90 s (RB) and 20 s (RQ), see later.  This step is scheduled to take maximum 220 s.  If needed, some tests can be added with a linear ramp down. Step 6: Ramp down from 1000 A to 0 A with -100 A/s  This step is scheduled to take 10 s. Typical current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 4 5 6

11. The ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Using h=5 W/K/m 2 for insulated bus and h=20 W/K/m 2 for non-insulated bus.

12. RB (Voltage and power for one sector) Hugues will discuss if the converters can power the circuits in this way. Bernardo will discuss if the current leads can operate with T bottom up to 80 K. Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

13. RB (V and dV/dt for one segment of 38 m) Jens will show how the QPS works with these strongly varying V and dV/dt Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012  V≈1 V  (dV/dt)≈25 mV/s

14. RB (power for one sector) Krzysztof/Serge will show the expected cryogenic behaviour  =280 MJ  =130 MJ Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

15. RQ (Voltage and power for one sector) Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

16. RQ (V and dV/dt for one segment of 115 m) Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

17. RQ (power for one sector)  =60 MJ  =50 MJ Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

18. Main (technical) issues: Opening of the diodes (without tripping the converter). Protection with a strongly changing ‘background’ V and dV/dt. Possible ‘sunglasses’ at the start of the test. Protection of the HTS part of the current lead. Powering, especially the 60 s with I>6.5 kA. Cryogenic regulation of arc and DFB, and helium pressure. Heat transfer between bus/diode and GHe. Fast data acquisition and analysis Ultimate current cycle Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

19. Test sequence for the type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

20.  Check if the diodes conduct, and measure the forward voltage.  Measure the inductance of the circuit.  Measure the resistance of the busbar segments and the diode leads. Very high resistances can already be detected.  Check the correct functioning of the QPS.  Check a QPS trigger on the V threshold.  Check a QPS trigger on the dV/dt threshold.  A series of measurement runs at increasing current and MIIt’s is foreseen to avoid as much as possible a very fast thermal runaway.  The first tests will be carried out with small currents in order to: Test sequence for the type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012  Quench thresholds will be set to low values for the first runs and will be increased during the test campaign.  All measurement runs will be compared to simulations, and a next run will only be started once all signals are understood.  Histograms during the analysis will help us to identify the outliers.

21. dI/dt up (A/s) I (kA) t top (s) DecayMIIt’s (10 6 A 2 s) V (mV) (dV/dt) (mV/s) T bus,max (K) Q (MJ) 1a42140 Exp,  =88 s 5414-0.15/0.012112 2a125240 Exp,  =88 s 31915/29-0.28/0.042333 3a292420 Exp,  =88 s 106021/65-0.40/0.412964 3b292470 Exp,  =88 s 186031/92-0.57/0.643598 4a458624 Exp,  =88 s 257044/133-0.79/2.039111 4b458646 Exp,  =88 s 336064/194-1.15/3.045138 4c458670 Exp,  =88 s 422090/295-1.8/4.752170 4d458694 Exp,  =88 s 509090/450-2.7/7.260209 5a625842 Exp,  =88 s 5740128/623-3.7/1367221 5b625854 Exp,  =88 s 6510128/894-5.4/1977265 6a958122 Exp,  =88 s 7190225/1227-7.4/1987296 Test sequence for the RB type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Assuming adiabatic conditions

22.  Other runs will probably be added during the campaign, based on test results & analysis.  If, during the type test, the equivalent MIIt’s cannot be reached, then an ‘as-good-as-possible’ qualification run will be performed going to the same current but for a shorter time or a smaller . This gives at least the possibility to assess the contact resistances in the diode leads.  The test sequence of the RQ will be similar with about 15 runs with MIIt’s increasing up to 2160 10 6 A 2 s.  The test sequence of the CSCM after LS1 will be based on the results of the type test. Test sequence for the type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

23. Risk assessment Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012  Risk of the CSCM type test  Risk of the CSCM after LS1.  Risk of not doing the CSCM

24. Risk of the type test 1 Problems that could happen at the first test cycles but will be solved before performing tests at higher current  The power converter does not follow the requested current cycle.  The QPS does not work properly. 2 Problems that could occur at higher currents, but can probably be avoided/limited by the staged increase in MIIt’s per test run.  Equipment (converter, diode, lead, …) gets damaged due to overvoltage, overpressure, high temperature, helium flow, … Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 3 Problems that cannot be completely avoided.  The QPS does not detect the voltage run-away (also note that the diode lead protection has no redundancy).  The voltage runaway is too fast to avoid a burn-out.  One of the (bolted) connections suddenly (partially) opens.

25. In case of a local burn-through of a busbar joint at full current, an arc will occur, and the current will decay semi-linearly. As compared to the 2008 accident the energy dissipation in the arc is roughly 10000x smaller. Theoretically it takes 5 kJ to melt 1 cm 3 of copper. So 25 kJ can melt 1.6 cm of RB bus, and 34 kJ can melt 3.4 cm of RQ bus. It is therefore almost sure that an arc in the RB or RQ circuit will cause damage which is only limited to the bus itself, and will not make a hole in the M-line, or damage other equipment. Risk of the type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 RBRQ dI/dt [kA/s]-60 to -50-57 to -19 t [s]0.220.35 Q arc [kJ]2534

26. In case of a local burn-through of a diode lead at full current, the current will be forced in the normal conducting magnet, and decay semi-exponentially. The MIIt’s needed for detection and switch-off of the converter have to be added (about 3 MA 2 s for 20 ms). The energy dissipated in the cable of the magnet is relatively small and will not cause the cable to burn through. Risk of the type test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 RBRQ dI/dt [kA/s]-194 to -44-140 to -13 t [s]0.120.22 MIIt’s [10 6 A 2 s] 3.87.6

27. Risk of a CSCM test after LS1 The type test will (hopefully) have resolved all possible risks related to the hardware. Voltages will always remain below 400 V. The consolidation during LS1 will have resolved all the defective 13 kA joints and strengthened the contacts at the connection plates of the quad diodes. The QPS should therefore never trigger except if there is still a weak spot in the circuit. F such a weak point is detected too late it could possibly cause a burn-through of the circuit and arcing, but the consequences will be small. Anyhow, it will be much better to see the defect during the CSCM then during operation… Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

28. RB Number of training quenches to reach 6.5 TeV (11 kA)40 Number of training quenches to reach 7 TeV (11.85 kA)800 Number of MB quenches during normal operation at I>10 kA4/year RQ Number of training quenches to reach 6.5 TeV (10.4 kA)4 Number of training quenches to reach 7 TeV (11.2 kA)16 Number of MQ quenches during normal operation at I>10 kA2/year PS: I neglect all quenches at I<10 kA (which includes also almost all the secondary MB quenches) The probability of having defective 13 kA joints after LS1 is negligible. I will focus therefore on defects in the diode leads which have to conduct the current in case of magnet quenches. I will use the following estimates (for the entire machine): Risk of not doing the CSCM test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

29. The diode leads have never been tested at high current and it cannot be guaranteed that all diode leads can handle a 12 kA discharge without overheating. As an example I will assume: Probability of a defective MB diode lead: 0.01% Probability of a defective MQ diode lead: 0.01% Probability for overheating RB training to 6.5 TeV1% (40 * 2 * 0.01%) training to 7 TeV15% (1- (99.98/100) 800 ) normal operation0.1%/year (4 * 2 * 0.01%) RQ training to 6.5 TeV0.2% (4 * 2 * 2 * 0.01%) training to 7 TeV0.6% (16 * 2 * 2* 0.01%) normal operation0.1%/year (2 * 2 * 2* 0.01%) Risk of not doing the CSCM test Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

30. Risk assessment: Conclusion Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Risk of the CSCM test after consolidation The probability for damage (P2) should be very small. The consequences (C2) are small and might lead to some delay of LS1. Risk=PxC  0 Probability for circuit opening (P)Consequences (C) Risk =P*C CSCM type testNot negligibleVery small  0 CSCM test after consolidation Very smallSmall  0 Operation without doing CSCM Very smallVery large> 0

31. CSCM type test in one sector at the start of LS1 CSCM in remaining 2 sectors CSCM in the first 6 consolidated sectors Stop tests Yes No Yes No Yes Run LHC at <6.5 TeV CSCM in remaining 2 sectors later Run up to 7 TeV Warm-up, repair, cool-down No Test successful ? Defects found? Warm-up, repair, cool- down Yes Run up to safe energy Warm-up, repair, cool-down Possible CSCM test strategy Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012

32. Planning CSCM type test From M. Bernardini

33. CONSTRAINT: powering tests have to be performed in 3 sectors in parallel Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Planning CSCM in 6 sectors after consolidation From M. Bernardini

34.  The CSCM is a powerful tool to qualify the bus and bypass part of the main circuits, especially the diode leads which have never been tested at high currents.  A CSCM type test at the beginning of LS1 is necessary as a proof-of- principle. The risk of such a test is very small, mainly due to a staged approach of the test campaign, with slowly increasing MIIt’s per test.  To validate the type test, runs have to be performed up to at least 10 kA, but preferably up to 12 kA. At least 2 thermal runaways should be planned in order to test the proper functioning of the QPS.  The decision to do the CSCM after LS1 should be made directly after the type test, and requires more resources. Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Conclusion 1/2

35.  The risk associated with a CSCM after LS1 is very small, and mainly limited to sudden increases in contact resistances. After consolidation such weak points should of course not anymore be present, and if they are still present it is better to find them with the CSCM than during operation.  If the SM18 tests show that the HTS leads cannot be safely run with 20-80 K at the bottom, then the CSCM can still be done while trying to keep the DFB’s cold (<9 K). After consolidation of the joints, the main purpose of the test is the diode leads so having a superconducting bus close to the DFB’s is not a problem.  If successful and useful, one could envisage to perform the CSCM test on a more regular base in the coming 20 years. Arjan Verweij, TE-MPE, CSCM review 14 Nov 2012 Conclusion 2/2