1. Silicon-On-Insulator Technology Submitted By :- Sweta Singh 0401212018 7 th Sem,ENTC(A)

2. Talk Flow Brief about MOSFETs Issues relating MOSFETs SCEs Sub-threshold current Introduction to SOI SOI Fabrication SOI MOSFETs How SOI solves SCEs? Application Constraints Industry Status Conclusion References

3. Brief about MOSFETs MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are four-terminal voltage-controlled devices. Two types depending on what type channel is formed==>  nMOS(n-type channel)  pMOS(p-type channel) Adapted http://ams.com

4. Contd… Modes of operation :  cut-off region  linear region  saturation region Current Equation is: for V DS <(V GS –V T0 ) for V DS >=(V GS –V T0 )

5. Issues about MOSFETs Limitation on scaling Short-Channel Effects Parasitic Capacitances & Latch-up Scaling:some device dimensions are scaled down with each new generation but some of them can’t be arbitrarily scaled due to physical limitations. Latch-up:generation of low impedance path in CMOS such that it virtually short circuits power supply to gnd,thus causing permanent device damage due to excessive current flow.

6. Short-Channel Effects(SCE S ) A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junction. The short-channel effects are attributed to two physical phenomena:- 1.the limitation imposed on electron drift characteristics in the channel. 2.the modification of the threshold voltage due to the shortening of channel length. Adapted from http://citeseer.ist.psu.edu

7. Contd… Following are some short-channel effects imposed by small geometry devices: 1. drain-induced barrier lowering and punch-through 2. Impact ionisation 3. velocity saturation 4. surface scattering 5. oxide breakdown 5. hot electrons Effect of DIBL on Threshold voltage(Vth) 

8. Sub-Threshold Current Sub-threshold leakage current is the current that flows between the source and drain of a MOSFET under the condition (VGS<VT0). Current flows in the channel because potential barrier of channel is reduced due to increase in the drain-to-source voltage. In the past, the subthreshold leakage of transistors has been very small, but as transistors have been scaled down, subthreshold leakage can compose nearly 50% of total power consumption. Scaling reduces the threshold voltage in the same proportion. As threshold voltages are reduced, subthreshold. leakage rises exponentially.

9. Sub-Threshold slope By measuring how many millivolts MOSFETS take to change the drain current by one order of magnitude, i.e. one decade of current on a logarithmic scale,this characteristic is called the subthreshold slope. In MOSFET, the subthreshold swing is limited by thermal voltage and it is 60 mV/decade at room temperature. This value ultimately determines how low in power your device technology can be. SOI (IBM) -- subthreshold slope of 75-85 mV/decade.

10. Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide.

11. Introduction The first implementation of SOI was announced by IBM in August 1998. Implementation of SOI technology is one of the manufacturing strategies employed to allow continued miniaturization of microelectronic devices. Performance gains 20-35% when design is moved from bulk Si to SOI. Benefits of SOI technology relative to conventional silicon (bulk CMOS) :-  Lowers parasitic capacitance due to isolation from the bulk silicon, which improves power consumption and thus high speed performance.  Reduced short channel effects.  Reduced Short channel effects

12. Contd…  Better sub-threshold slope.  No Latch up due to BOX(buried oxide).  Lower Threshold voltage.  Reduction in junction depth leads to low leakage current.  Higher Device density. Adapted http:// www. ibis.com/simox.htm

13. SOI Fabrication Different methods used to fabricate SOI wafers:  SIMOX(Separation by IMplantation of OXygen) -uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO 2 layer. Adapted http:// www. ibis.com/simox.htm

14. Contd..  Wafer Bonding-One prominent example of the wafer bonding process is the Smart Cut. The insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer. Generally,wafers manufactured by this method have thicker silicon layer above the insulator layer than those produced by the SIMOX process.

15. SOI MOSFETs Two types of SOI-devices:  PD-SOI(Partial Depletion Type)  FD-SOI(Complete Depletion Type)  FD SOI do not enjoy the ease of manufacturing as compared to PD SOI.  Reason for this is that FD SOI exhibit increased SCEs than PD SOI. Fully Depleted SOIPartially Depleted SOI Adapted frederic.hameau@cea.fr

16. How SOI solves SCEs? SOI have higher immunity to SCEs as compared to bulk MOSFETs. This is due to the drain-source junction depth which is 50-100nm in 0.25-0.35 micro-meter SOI technology,extremly shallow compared to bulk MOSFETs. silicon film thickness of 10-15nm. Body doping also reduces SCEs.

17. Application SOI has opened the door for opportunities in the low- power arena. Used in wireless technology which requires the use of high resistivity substrates. Used in case of faster speed operations. Microprocessors are built with SOI as substrate. SOI is an attractive alternative for low-voltage digital CMOS logic, microprocessors, memories, sensors and integrated optical electronics.

18. Constraints Major challenge in SOI devices is the Floating body Effects. Here the body floats i.e.,electrically isolated,therefore substrate- source bias voltage is not fixed and hence device threshold fluctuates. Among them Kink effect is noticable,more in case of PD-SOI devices Due to this there is a sudden increase in drain current with discontinuity resulting in worsening of the differential drain conductance. Other effects include passgate leakage and history effect. Hence most of the effort in mapping bulk Si circuits to SOI is spent fixing these effects-a challenge.

19. Industry Status Soitec, the world's leading supplier of SOI wafers signed an agreement with AMD for a long-term supply of UNIBOND SOI wafers in 2005. The company uses the Smart cut Process. SOI currently represents some 3-4% of the total wafer market, and this is expected to rise to 10% by the end of the decade. Total SOI wafer market is expected to approach the US$1 billion mark by 2009. Microsoft's Xbox 360 and Sony's PlayStation 3 have one thing in common and that is the latest multiprocessor servers from IBM, Sun and Dell.

20. Contd.. All of them use chips made with silicon on insulator (SOI) technology. The Pioneer company among them is the IBM because it was only due to their hard work and faith in SOI technology that today it has become an integral part of semiconductor devices. Also SOI substrates have been proved in volume manufacturing at chip manufacturers such as IBM, Freescale and AMD. Motorola is said to be using the material at some level for wireless communication chips.

21. Conclusion Today SOI is being used by many companies despite of the fact that it is expensive and bringing it into the mainstream of Si technology has been challenging. However,as we move to the 0.1micro-meter generation and beyond,SOI offers the total solution to problems of bulk-Si substrate and SOI will be the technology of choice.

22. References [1]Sung-Mo Kang,Yusuf Leblebici,”CMOS Digital Integrated Circuits:Analysis and Design,”Tata Mcgraw-Hill.Third edition,2003. [2] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Dordrecht, Netherlands, 1991. [3] http://www.ibis.com/simox.htm [4]http://www.freescale.com/webapp/sps/site/overview.jsp?nodeI d=0121000303#soi