1. Tri-Gate와 Spacer의 상관관계에 대한 특성연구 Week 15th 200801190 정성인 200901037 백근우*
Final Presentation
Tri-Gate와 Spacer의
상관관계에 대한 특성연구
Week 15th
정성인
백근우*
김기연
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2. INDEX 01) Intro 02) Body 03) Remarks
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3. 01. Introduction
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4. Multiple Gate Specification Limitation Equipment
Trend in Semiconductor
- Super-high Speed
- Super-large Integration
- Low-power Technology
2. Problems with SCE(Short Channel Effect)
- Reduction of sub-threshold voltage
- Reduction of mobility
- Increase of leakage current
- Increase of resistance between source and drain
3. Ideal Model
- Multiple Gate(MuGFET)
- It has great performance on gate control
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5. Multiple Gate Specification Limitation Equipment
월 인텔 아이비브릿지 출시
월 인텔 하스웰 출시
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6. Multiple Gate Specification Limitation Equipment
What is ‘Tri-Gate’?
Even though GAA(Gate All Around) is the most ideal for transistors, it’s difficult to produce in quantity due to processing. Tri-Gate on nano scale is not only easier to produce, but also has similar properties with GAA. Tri-Gate has great performance on gate control, but it need to resolve some problems with short channel effect, hot carrier effect or series resistance.
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7. Multiple Gate Specification Limitation Equipment
About Spacer
Spacer is originated at the shave the film of semicon. It makes the space between the films to secure channel length of transistor or the pressure of junction.
The properties we’re going to study on
- The trait changes with spacer
- The trait changes with the length
- Optimization of the best fin width
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8. Multiple Gate Specification Limitation Equipment
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9. Multiple Gate Limitations
Multiple Gate Specification Limitation Equipment
Vd • Vg, Stress
Channel Length, Width
Limitations
Temperature, humidity or vibration
The length and width of Gate
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10. Multiple Gate Specification Limitation Equipment
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11. Multiple Gate Specification Limitation Equipment
<Probe Station>
<Parameter Analyzer>
Use four probes.
Apply voltage to all probes and each probe measures currents.
Usually, it is better to use SMU probe as Gate.
It is possible to analysis the properties of semiconductor using B1500.
It is required to observe the monitor to check normal operations.
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12. Equipment Multiple Gate Specification Limitation Equipment
<Probe Station>
Top / Bottom
(micro)
Top / Bottom
Right / left
the front / the rear
※Tip
After contacting on device, it is possible to move with only adjustment of microscope.
Adjustment of right and left
Adjustment of the front and the rear
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13. Equipment Multiple Gate Specification Limitation Equipment
<Probe Station>
Right/left on Wafer Chuck
Apply voltage using B1500 and measure it.
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14. Multiple Gate Specification Limitation Equipment
<1>
<2>
1 equipment is called Fiber Optic and provides the light when measurements.
2 equipment fastens the device and probe holder.
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15. Multiple Gate Specification Limitation Equipment
C-V Equipment for measurement
3. Start
1.Power
2.Range of temperature
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16. 02) Body

17. Explanation Measurement
LDD Structure
Explanation Measurement
Doping without spacer
Doping with spacer
R=(ρ*L)/A
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18. Explanation Measurement
GIDL(Gate Induced Drain Leakage)
Explanation Measurement
VG=-1.5V VS
VD=1V
GATE
Oxide e
Source( n+)
Drain( n+) h
Electric-field
P-Si
Vt decrease due to Body effect VB
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19. Explanation Measurement
DIBL(Drain Induced Barrier Lowering)
Explanation Measurement
On condition of transistor : VG >Vt
DIBL is the phenomenon that Vt decrease due to lowering of energy barrier.
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20. Explanation Measurement
Hot Carrier
Explanation Measurement
Hot Carrier is( VG >Vt :inversion condition ) the phenomenon that electric field from drain to source increases because the increment of Vd shorten the length of channel.
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21. Explanation Measurement
Hot Carrier
Explanation Measurement
Vt increases because elections in oxide are trapped due to hot carrier.
VG >Vt VS VD ↑
GATE
Oxide
Channel e e
Source( n+)
Electric-field
Drain( n+)
P-Si
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22. Explanation Measurement
Ids with Vgs
Explanation Measurement
Ids with Vgs
At Long channel, Vgs∝Id
∴Ids,v=1 > Ids,v=0.05
GIDL
Leakage current
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23. Explanation Measurement
Ids with Channel Length
Explanation Measurement
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24. Explanation Measurement
Ids with Spacer
Explanation Measurement
When the device doesn’t have spacer, the
Current is larger.
When the device has spacer, Ids decreases
Because series resistance increases.
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25. Explanation Measurement
DIBL measurement
Explanation Measurement
At 10nA,
Vgs difference = DIBL
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26. Explanation Measurement
DIBL with Length and Width
Explanation Measurement
LD=70nm(Width)
LE=50nm(Width)
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27. Explanation Measurement
Sub-thresh0ld slope Swing
Explanation Measurement
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28. Explanation Measurement
Hot Carrier measurement
Explanation Measurement
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29. Explanation Measurement
Hot Carrier (L=250nm, W=70nm)
Explanation Measurement
We can find that Id decreases and Vt increases due to stress.
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30. Hot Carrier (L=250nm, W=70nm)
Explanation Measurement
Ids decrease due to aging of the device as time goes by.
Gate Voltage
1.5 V
Drain Voltage
3.0 V
Time
1min, 5min, 10min, 20min, 30min, 40min, 50min, 60min
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31. Explanation Measurement
Hot Carrier Stress measurement (1)
Explanation Measurement
Gate Voltage
1.5 V
Drain Voltage
3.0 V
Time
1min, 5min, 10min, 20min, 30min, 40min, 50min, 60min
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32. Explanation Measurement
Hot Carrier Stress measurement (2)
Explanation Measurement
Gate Voltage
0.8 V
Drain Voltage
1.6 V
Time
1min, 5min, 10min, 20min, 30min, 40min, 50min, 60min
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33. Explanation Measurement
Series Resistance (1) - Theory
Explanation Measurement
Step for Rsd
2) Y-function Vg
𝑌=𝐼𝑑/ 𝑔𝑚
3) β=slope2/Vd
Slope=Rsd
β=slope2/Vd 𝜃𝑒
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34. Explanation Measurement
Series Resistance (2) with spacer
Explanation Measurement
Width
Rsd(Spacer)
Rsd
55nm
761Ω
650Ω
70nm
478Ω
190Ω
① When the device has spacer, Rsd increases due to n- doping of LDD structure.
② Rsd increases with the decrease of surface area as width decrease.
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35. Explanation Measurement
Series Resistance (4) with crystal direction
Explanation Measurement
(100)
(110)
Si 원자 수 ↓ ↑
Scattering
이동도
On Current
① W↑ A↑ ∴ R↓
② ∴ u(100) > u(110)
R(100) < r(110)
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36. Explanation Measurement
Series Resistance (5) with crystal direction
Explanation Measurement
① It is measured that Rsd decrease as channel width increase because surface area increase.
② It is measured that Rsd decrease as the degree of crystal direction increase because the current is large.
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37. 03. Remarks
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38. Evaluation Standard Copyright 2014. Semi. All Rights Reserved.
Evaluation items
Standard
Points
Achievement
1. How many the devices we use
Over 21 5
Used over 28 3
Under 17 1
2. A change of the current as Stress
Under 3%
Got about 6.25%
Under 5%
Under 10%
3. The number of experiments
Over 6
Have done 6
3- 5
Under 2
4. The understanding of measurements
Can explain very well
Studied a lot.
Can explain in some degree
Can hardly explain
Total
16/20
80%
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39. Evaluation Standard – in detail
How many devices we used?
- We’ve used kinds of the devices such as LD, LE, AR and JM as channel length(90nm, 100nm, 130nm, 150nm, 180nm, 250nm, 500nm)
Therefore, the sum of the devices we’ve used is 28 which is 4 times 7.
2. A Change of Current as Stress
Generally, a current tends to change as variables. When we consider stress as the only variable and compare before stress with after stress, then we get the change of Gate voltage which is about 0.05V to 0.1V. It’s 6.26% compared to 0.8V.
3. The number of experiments
We’ve measured ①the properties of Id-Vg, ②DIBL, ③Sub-threshold Swing, ④GIDL, ⑤Hot Carrier Stress and ⑥Series Resistance. Therefore, it’s 6 in total.
4. The Understanding
- All members in our team have done one’s parts, and we always studied together before we start new measurements. Therefore, we think we’re knowledgeable about our topics.
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40. Schedule Plan March April May June July August
Select a topic
Study for equipments
measurement for basic
DIBL,GIDL measurement
Hot Carrier Effect Simulation
Measure SCE
Specify a thesis
Work for a thesis and examine
: proceeded as a plan (100%)
: has been a little change (90%)
: didn’t proceed as a plan (60%)
: hasn’t proceeded yet ( - )
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41. Schedule Plan – in detail
Select topic : As we planned, we had considered our topic for two weeks with our professor and graduate student. (100%)
Study for Equipment: Since the middle of March, we’d started to study our equipments and run ourselves. (100%)
Measurement for Basic: Before we work on our graduation thesis, we needed knowledge for the basic properties of semiconductors, so we spent about two weeks, working on basic such as the properties of Id-Vg or Vt. (100%)
DIBL, GIDL Measurement: We measured DIBL, GIDL but it took a little longer than we expected. We spent about a month to get the results of these. The main reason was that our device is too old to show its proper properties. (90%)
Hot Carrier Effect: Even though 4th took a little longer, we kept 5th week’s plan. (100%)
Measure SCE: Originally, SCE was supposed to measure during first two months. Because we finished measurements for DIBL and GIDL , so we had to move on the next step. (60%)
Specify a thesis: here is our current step, and every measurements for our thesis have done. We’re going to work on composition for a thesis after this final presentation. (100%)
Total : 92.86%
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42. Abstract Spacer의 유무에 따른 Vg-Ids측정을 통하여 소자의 특성을 비교하였다.
첫째, L(100nm,130nm,180nm,250nm,500nm)별로 Vg-Ids 측정결과 L가 짧아질수록, Spacer가 없는 경우에 전류가 많이 흐르는걸 볼 수 있었다.
둘째, L,W에 따라 DIBL(Drain Induced Barrier Lowreing)을 측정한 결과 L이 클수록 Width가 짧을수록 DIBL이 작게 나타나는 걸 볼 수 있었다. 또한 L가 짧을수록 SS(Subthreshold Slope)가 크게 나타남을 확인 할 수 있다.
셋째, Spacer의 유무에 따른 Hot-Carrier와 Rsd(시리즈저항)을 측정 한 결과 Spacer가 있는 경우 Hot-Carrier열화 정도가 작게 나타나고 Rsd는 크게 나타났다.
넷째, 결정방향(100,110)에 따른 Drain Current 측정 결과 결정방향 100(45도)에서 큰 걸 알 수 있었다. 즉, 결정방향 100(45도)에서 Rsd가 작게 나타난다.

43. Work Division Division of a Work Geon Woo, Baek Gi Yeon, Kim
Sung In, Jung
1. Research materials
2. Analysis the change of properties as spacer
3. Composition of a thesis
Geon Woo, Baek
1. Analysis the properties of measurements
2. Proof or Give feedback for a thesis
3. Get references
Gi Yeon, Kim
1. Work on simulation
2. Analysis the best fin width
3. Composition of a thesis
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44. References 논문 <소자 레이아웃이 n-채널 MuGFET 의 특성에 미치는 영향>, 이승민 외 3명
논문 <Pi-Gate SOI MOSFET>, Jong-Tae Park 외 3명
반도체소자공학, Pierret 저, 교보문고,1997
(SPACER 관련자료)
(MuGFET 관련자료)
(첨부사진)
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45. !
THANK YOU
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