1. 01/10/2009 Y. Ikegami, KEK RD09, Florence1 Development of low-mass, high-density, hybrid for the silicon microstrip sensors in high track density environment A. Clark, D. Ferrere, M. Weber, S. G. Sevilla (Univ. of Geneva) K. Hara (Univ. of Tsukuba) Y. Ikegami, T. Kohriki, S. Terada Y. Unno (KEK)

2. 01/10/2009 Y. Ikegami, KEK RD09, Florence2 Introduction SLHC x10 higher luminosity of LHC Impact to silicon microstrip region Radiation damage Occupancy sensorn-in-p short strip module ? readout hybrid ? Short strips 2.4 cm Long strips 9.7 cm

3. 01/10/2009 Y. Ikegami, KEK RD09, Florence3 Integration concepts Tight cooling contact, Low-mass, Automatic assembly, … Hybrid glued to sensors. These glued to bus tape. This glued to cooling substrate. Module modularity production, QA, repairs, etc. ➡ parallel tasks reparability and replaceability possibility of Z-overlapping Stave

4. 01/10/2009 Y. Ikegami, KEK RD09, Florence4 Module Current SCT barrel module Next SCT module Double side module Sensor size10cm x 10cm Strip length2.4cm n-in-p 1280 strips (74.5um pitch) 4 hybrids (separated) with 20 ABCN ASICs each bridging over the sensors Double side module Sensor size 12cm x 6cm Strip length12cm p-in-n 768 strips (80um pitch) 1 hybrid (wrap-round) with 12 ABCD3T ASICs bridging over the sensors

5. 01/10/2009 Y. Ikegami, KEK RD09, Florence5 Wire bonding scheme A direct wire bonding scheme between sensors and FE chips will be adopted to eliminate pitch adaptors. The maximum fanning angle amounts to 16 degrees. We have confirmed by making a wire bonding test module.

6. 01/10/2009 Y. Ikegami, KEK RD09, Florence6 Thermal FEA simulations (Geneva) Detailed FEA simulations ➡ thermal performance 3D model (ANSYS, Abaqus) Parameters under study: power/chip cooling temperature convection/radiation (gas temperature) thermal grease thickness

7. 01/10/2009 Y. Ikegami, KEK RD09, Florence7 Thermal test module We have been investigating thermal property of module with a thermal test module, in order to validate thermal FEA simulations.

8. 01/10/2009 Y. Ikegami, KEK RD09, Florence8 Super-Module Insert modules into a frame: Super-module Super-module contains cooling piles, power cables, optical fibers and monitoring cables. 2 proposals for module integration into cylinders: Lateral insertion (KEK): Installation of the Super-Modules, cylinder by cylinder End-insertion (Geneva): Barrel structures can be assembled before the Super-Modules are integrated.

9. 01/10/2009 Y. Ikegami, KEK RD09, Florence9 Circuit Diagram of Hybrid The hybrid is loaded with 20 FE ASICs (ABCN), each having 128 readout channels. The first hybrid was developed by Univ. of Liverpool. In order to shorten a production period, several functions of hybrid were limited. KEK hybrid provides the full specifications operation of ABCNext chips. redundancy operation two sets of bus lines bypass scheme for dead chip various powering schemes individual powering for Vcc (2.2V) and Vdd (2.5V) voltage regulator for Vcc two types of shunt regulator for serial powering application

10. 01/10/2009 Y. Ikegami, KEK RD09, Florence10 Circuit Diagram of Hybrid The hybrid is loaded with 20 FE ASICs (ABCN), each having 128 readout channels. The first hybrid was developed by Univ. of Liverpool. In order to shorten a production period, several functions of hybrid were limited. KEK hybrid provides the full specifications operation of ABCNext chips. redundancy operation two sets of bus lines bypass scheme for dead chip various powering schemes individual powering for Vcc (2.2V) and Vdd (2.5V) voltage regulator for Vcc two types of shunt regulator for serial powering application

11. 01/10/2009 Y. Ikegami, KEK RD09, Florence11 Front-end ASIC ABCNext front-end ASIC (250 nm IBM CMOS6 technology) Binary architecture, 128 channels Analog blocks: Preamplifier, shaper, discriminator (differential threshold) Individual threshold trimming correction per channel Internal calibration circuit Positive and negative signal polarities Linear voltage regulator on-chip, shunt regulator Digital blocks: Pipeline memory length of 6.4 µs Derandomizer buffer (42 events length) Two-clocks schema to allow different readout rates (40/80 MHz) Block diagram of the ABCN

12. 01/10/2009 Y. Ikegami, KEK RD09, Florence12 Layout of Hybrid Layers Layer 2 (inner) Layer 1 (front side) Layer 4 (back side) Layer 3 (inner) L1 and L2 include the main circuit patterns for ASICs with redundancy lines. L3 and L4 are mainly for the power distribution and grounding, respectively. To evaluate grounding scheme, analog and digital ground can be separated.

13. 01/10/2009 Y. Ikegami, KEK RD09, Florence13 Hybrid design rule Back side Front side Hybrid after mounting FE chips, R C components and a 0.8mm pitch miniature connector at the right end. Min. Line Width0.1mm Min. Gap0.09mm Min. Via-hole0.1mmΦ Min. Thr.-hole0.3mmΦ Taiyo Industrial Co., LTD 136mm x 28mm 0.260 0.165

14. 01/10/2009 Y. Ikegami, KEK RD09, Florence14 Hybrid construction The hybrid backed with a 400 um thick and 112 mm wide carbon-carbon sheet is designed to bridge over the silicon sensor avoiding any interference to the sensor surface. The carbon-carbon bridge having large heat conductivity of 670W/m/K transfers the generated heat to the heat sink located at the legs of the bridge. The total weight (excluding electrical components) is 4.25 g, having 0.00425 X 0 equivalent radiation lengths.

15. 01/10/2009 Y. Ikegami, KEK RD09, Florence15 Button Plating I also called pads-only plating or spot plating, limiting an area of the via- and through-hole plating The total weight of bare FPC is 1.91g. The weight considerably decreased to 1.91g from 3.09g by button plating.

16. 01/10/2009 Y. Ikegami, KEK RD09, Florence16 Button Plating II Our target for through-hole diameter is the minimum of 0.3mmΦ (standard 0.6mmΦ). We ordered 4 sheets (8 pieces/1sheet), as first lot. We obtained one good flex circuit out of 32. A major problem is come form misalignment of layer stacking. We ordered one more sheet w/o button plating. We obtained 3 good flex circuits. Improvement by the maker has been performed, we obtained 10 good flex circuits in the second lot. We can receive the stable supply of flex circuits w/ button plating.

17. 01/10/2009 Y. Ikegami, KEK RD09, Florence17 DAQ system We have two DAQ systems. Modified current SCT DAQ system Reuse the current resources However, the data transfer rate is limited to 40MHz. New NI DAQ system (Geneva) NI PXI-6562 6 channels digital WF generator/analyzer 200/400 Mbps per channel SDR/DDR LVDS signals, per-channel direction control Software: LabVIEW 8.6 configuration files through XML (+schema) scripted generation and multi-record acquisition

18. 01/10/2009 Y. Ikegami, KEK RD09, Florence18 Electrical Tests Results I Gain uniformity The average gain is about 100mV/fC. Quite uniform distributions were obtained in two sites. There was no difference by having button plating or not. Gain [mV/fC] KEK Geneva

19. 01/10/2009 Y. Ikegami, KEK RD09, Florence19 Electrical Tests Results II Uniformity of Noise (ENC) The average ENC is about 400e. Quite uniform distributions were obtained in two sites. There was no difference by having button plating or not. ENC [e] KEK No.2 Geneva

20. 01/10/2009 Y. Ikegami, KEK RD09, Florence20 Electrical Tests Results III In order to investigate a change of ENC with a detector capacitance, we connected external capacitances with the input of amplifiers, and measured ENC. The first stage of amplifier current was changed into 81uA (red), 140uA (green) and 198uA (blue). ENC measurements were performed at three sites independently and the results were in agreement. Detector capacitance

21. 01/10/2009 Y. Ikegami, KEK RD09, Florence21 Test Module Preparing The characteristics of the readout ASIC are evaluated with different length microstrip sensors connected to the input of the ASIC. Wire bonding is completed soon and noise study will be started.

22. 01/10/2009 Y. Ikegami, KEK RD09, Florence22 Module Program Geneva and KEK produce 4 modules each n-in-p sensors 10cm x 10cm KEK hybrids (flex circuit x62) ABCNext 250 nm chips Common design and close assembly procedures and jigs Main objectives: prove functionality mechanical precision not a primary target focus on electrical/thermal performance Module test-box: single and 4-modules test-boxes (Geneva) Irradiations Module to be irradiated at CERN PS comparison performance pre and post-irradiation

23. 01/10/2009 Y. Ikegami, KEK RD09, Florence23 Summary We have fabricated a low-mass, high-density, hybrid which provides the full functionality of the ABCNext full chips. The weight of flex circuit considerably decreased to 1.91g from 3.09g with button plating. The electrical tests on the hybrid level are mostly completed. The module tests are planned to start soon.