1. 1 Interconnect and Packaging Lecture 2: Scalability Chung-Kuan Cheng UC San Diego

2. 2 Outlines I.Trends of Interconnect and Packaging II.Scalability References

3. 3 I. Trends of High Performance Interconnect and Packaging Year2011201520202025 D1/2 Pitch, nm4025147 #metal layers121314- Ave permittivity2.992.782.231.99 M1 pitch, nm/AR76/1.842/1.924/2.013/2.2 M1 cap, pF/cm1.9-2.11.8-21.6-1.81.5-1.8 RC delay, ns/mm3.42915.16456.834224.749 Int pitch, nm/AR76/1.842/1.924/2.013/2.2 Int cap, pF/cm1.7-1.91.6-1.91.3-1.61.1-1.5 RC delay, ns/mm3.16813.74148.203192.495 Glob pitch, nm354-190482-190702-1901125-190 Glob cap, pF/cm2.0-2.31.8-2.21.4-1.81.2-1.6 RC delay, ns/mm0.9994.01214.81467.913

4. 4 I. Trends of High Performance Interconnect and Packaging Year200520102011201520202024 D1/2 Pitch, nm 80454025149 Chip size, mm 2 310 140-750 Pin count3,4004,009720-5094880-61911050-79021212-9148 Cents/pin1.781.370.57-1.480.46-1.210.35-0.940.30-0.77 On-chip (MHz) 5,17012,00 0 6,3308,52012,36015,410 Off-chip (MHz) 3,12510,00 0 12,00030,00055,00075,000 Power Density w/mm 2 0.540.640.7-0.550.9-0.751.15-11.35-1.20

5. 5 I. Trends On-Chip Interconnect Delay (5-40 times of Speed of Light 5ps/mm) Power Density (> ½) Clock Skew: Variations (5GHz) Off-Chip Interconnect and Packaging Number of pins (limited growth) Wire density (scalability) Speed and distance of interconnect

6. 6 I. Trends On-chip Global Interconnect trend Concerns: Speed, Power, Cost, Reliability

7. 7 I. Trend Scalability Latency, Bandwidth Attenuation, Phase Velocity Distortion Intersymbol Interference, Jitter, Cross Talks Clock Distribution Skew, Jitter, Power Consumption IO Interface Density Impedance Matching Cross Talks, Return loops

8. 8 II. Scalability: Interconnect Models Voltage drops through serial resistance and inductance Current reduces through shunt capacitance Resistance increases due to skin effect Shunt conductance is caused by loss tangent

9. 9 II. Scalability: Interconnect Models Telegrapher’s equation: Propagation Constant: Wave Propagation: Characteristic Impedance

10. 10 II. Scalability of Physical Dimensions R= ρ/A = ρ/(wt) Z= ¼ (µ/ε) 1/2 ln (b+w)/(t+w) C= vZ L= Z/v b w t ρ: resistivity of the conductor µ: magnetic permeability ε: dielectric permittivity v: speed of light in the medium

11. 11 II. Scalability of Physical Dimensions Resistance: Increases quadratically with scaling, e.g. ρ=2µΩ-cm R=0.0002 Ω/µm at A=10µmx10µm R=0.02 Ω/µm at A=1µmx1µm R=2 Ω/µm at A=0.1µmx0.1µm Characteristic Impedance: No change Capacitance per unit length: No change Inductance per unit length: No change

12. 12 II. Scalability of Frequency Ranges 1.RC Region 2.LC Region 3.Skin Effect 4.Loss Tangent

13. 13 II. Scalability of Frequency Ranges 1. RC Region e.g. on-chip wiresR=2ohm/um (A=0.01um 2 ) L=0.3pH/um, C=0.2fF/um R/L=6.7x10 12

14. 14 II. Scalability of Frequency Ranges: RC Region Elmore delay model with buffers inserted in intervals l tr : length from transmitter to receiver l: interval between buffers r n : nmos resistance c n : nmos gate capacitance c g =(1+g)c n, g is pn ratio. r w : wire resistance/unit length c w : wire capacitance/unit length f: c d /c g l l tr

15. 15 II. Scalability of Frequency Ranges: RC Region Elmore delay model with buffers inserted in intervals Optimal interval Optimal buffer size Optimal delay

16. 16 II. Scalability of Frequency Ranges Example: w= 85nm, t= 145nm Optimal interval Optimal buffer size Optimal delay r n = 10Kohm,c n =0.25fF,c g =2.34xc n =0.585fF r w =2ohm/um, c w =0.2fF/um

17. 17 II. Scalability of Frequency Ranges: RC Region Year (On-Chip) 200520102015 r n c n (ps)0.860.390.18 r w c w (ps/mm) * 2846161510 l (um)1687733 D (ps/mm)9695101 *no scattering, p=2.2uohm-cm

18. 18 II. Scalability of Frequency Ranges: RC Region Device delay, r n c n, decreases with scaling Wire delay, r w c w, increases with scaling Interval, l, between buffers decreases with scaling In order to increase the interval, we add the stages of each buffer.

19. 19 II. Scalability of Frequency Ranges 2. LC Region

20. 20 II. Scalability 3. Skin Effect Skin Depth:

21. 21 II. Scalability 3. Skin Effect Skin Depth: e.g. 0.7um @ f=10GHz, ρ=2uΩ-cm For 100umx25um R DC =0.000008Ω/um= 8Ω/m R= 0.000114Ω/um=114Ω/m

22. 22 II. Scalability 4. Loss Tangent

23. 23 References E. Lee, et al., “CMOS High-Speed I/Os – Present and Future,” ICCD 2003. http://www.itrs.net/ Ling Zhang, Low Power High Performance Interconnect Design and Optimization, Thesis, UCSD, 2008. G.A. Sai-Halasz G.A. "Performance Trends in High-End Processors,“ IEEE Proceedings, pp. 20-36, Jan. 1995. M.T. Bohr, “Interconnect scaling-the real limiter to high performance ULSI” Electron Devices Meeting, 1995., International 10-13 Dec. 1995 pp.241 – 244.