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© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Introduction Purpose  This course provides an overview of the CPU architecture of Renesas.

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Presentation on theme: "© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Introduction Purpose  This course provides an overview of the CPU architecture of Renesas."— Presentation transcript:

1 © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Introduction Purpose  This course provides an overview of the CPU architecture of Renesas H8S series 16-bit microcontrollers (MCUs) Objectives  Review the H8S general-purpose register set and control registers  Learn about the data format in registers and memory and access timing  Understand the CPU’s instruction set, addressing modes, memory map, data access timing, and accesses to peripheral registers Content  19 pages  3 questions Learning Time  30 minutes

2 © 2008, Renesas Technology America, Inc., All Rights Reserved 2 Features of H8S Architecture  H8S/2000 or H8S/2600 CPU core  Concise, optimized instruction set  Eight addressing modes  16MB address space  General-purpose registers D/A SCI WDT H8S/2000 CPU core I/O TPU PPG 8-bit Timer INTC Bus Contr. A/D CPG DMAC ROM (384KB) RAM (32KB) DTC Example: H8S/2329B  High Performance:  Fast CPU operating speed (up to 35MHz, device dependent)  Single-cycle instruction execution  Benchmark speed: up to 15.1 MIPS (Dhrystone v1.1 at 33MHz)

3 © 2008, Renesas Technology America, Inc., All Rights Reserved 3 Full Upward Compatibility H8S/2600 CPU 69 Instructions 8 address modes H8S/2000 CPU 65 Instructions 8 address modes H8/300H CPU 64 Instructions 8 address modes H8/300L CPU 57 Instructions 8 address modes Code Compatible moving up and down  Four MAC instructions  H8S/2400 and H8S/2600 product groups  Multiple Load/Store instruction  H8S/2100, H8S/2200, H8S/2300, and H8S/2500 product groups  8/16/32 bit arithmetic instructions  Enhanced push and pop instructions  Signed/Unsigned MULT/DIV instruction  Signed/Unsigned extension instruction  Enhanced trap exception handling  8/16-bit arithmetic and logic instructions  Unsigned MULT/DIV instructions  Powerful bit manipulation instructions

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5 © 2008, Renesas Technology America, Inc., All Rights Reserved 5 General-Purpose Registers 633241 310 (Sign extension)MACH MACL MAC Registers ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) 1507070 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers Control Registers 7 6 5 4 3 2 1 0 EXR T - - - - I2 I1 I0 310 PC 2315 H8 CPUs All CPUs in H8 series include the same basic register set, allowing complete compatibility. H8/300L Uses 8 general-purpose registers as 8 and 16 bits. PC is 16 bits wide. H8/300H Uses 8 general purpose registers as 8, 16 and 32 bits. PC is 24 bits wide. H8S/2000 Uses 8 general purpose registers as 8, 16 and 32 bits. PC is 24 bits wide. H8S/2600 Uses 8 general purpose registers as 8, 16 and 32 bits. PC is 24 bits wide. Hardware MAC included. 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C

6 © 2008, Renesas Technology America, Inc., All Rights Reserved 6 Register Configuration E0 R0 R0HR0L ER0 E1 R1 R1HR1L ER1 E2 R2 R2HR2L ER2 E3 R3 R3HR3L ER3 E4 R4 R4HR4L ER4 E5 R5 R5HR5L ER5 E6 R6 R6HR6L ER6 E7 R7 R7HR7L ER7 (SP) 015 31 7  Eight 32-bit registers (ER0 - ER7)  Sixteen 16-bit registers (E0 - E7 and R0 - R7)  Sixteen 8-bit registers (R0H - R7H and R0L - R7L)

7 © 2008, Renesas Technology America, Inc., All Rights Reserved 7 Control Registers 23 0 PC CCR I UI H U N Z V C EXR T - - - - I2 I1 I0 Interrupt mask bit User bit Half-carry flag User bitNegative flag Zero flag Overflow flag Carry flag Trace bitI2 to I0: Interrupt mask bits

8 © 2008, Renesas Technology America, Inc., All Rights Reserved 8 7 6 5 4 3 2 1 0 - Don’t Care - 7 6 5 4 3 2 1 0 Upper Lower - Don’t Care - Upper Lower MSB LSB - Don’t Care - MSB LSB - Don’t Care - MSB LSB Data Format of General Registers Data format Word Data Long Data Data typeRegister Number 1-bit RnH 1-bit RnL 4-bit BCD RnH RnL 4-bit BCD Byte Data RnH RnL Rn En ERn 07 15 31 When ER7 (SP) is used as an address register to address the stack, the operand size should be word or long-word.

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10 © 2008, Renesas Technology America, Inc., All Rights Reserved 10 Data Format of Memory Data TypeAddress 1-bit Data Address “L” Byte Data Address “L Word Data Address “2M” Address “2M+1” Long-word Data Address “2N” Address “2N+1” Address “2N+2” Address “2N+3” 0 7 0 7 Big Endian Little Endian 7 6 5 4 3 2 1 0 MSB LSB Low Byte LSB MSB High Byte Low Byte LSB MSB High Byte Data Format 7 6 5 4 3 2 1 0 MSB LSB MSB High Byte Low Byte LSB MSB High Byte Low Byte LSB Data Format Word or long-word data must begin at an even address.

11 © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Eight Addressing Modes

12 © 2008, Renesas Technology America, Inc., All Rights Reserved 12 Examples of Addressing Modes Register Indirect with Post-Increment (Mode 4) MOV.W @R7+, R1 - Effective Address (EA) of the source operand is in the content of general register R7. - Transfer the data pointed by the content of R7 to the destination operand R1 - Increment the content of specified general register R7 by 2 for MOV.W or by 1 for MOV.B  Program Counter Relative (Mode 7) BSR h’40 - CPU pushes address of instruction next to BSR to the stack - Branch to  Destination Address = (PC) + 8-bit displacement Mode 7 is used in BCC and BSR instructions only. Auto post increment: Value added to general register depends on data size specified at the MOV instruction; i.e., it adds 1 for byte data, 2 for word data.

13 © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Basic Instruction Set Data transfer MOV, POP, PUSH, LDM, STM, MOVFPE, MOVTPE Arithmetic ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULX, DIVXU, DIVXS, CMP, NEG, EXTU, EXTS, TAS [MAC, LDMAC, STMAC, CLRMAC (H8S/2600 only) ] Logical AND, OR, XOR, NOT Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Branch BCC (conditional), JMP, BSR, JSR, RTS System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP, TRAPA Block data transfer EEPMOV Types of Operations Instructions Example of Instruction Format opccEA (disp)BRA d:16, etc.

14 © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Operating Modes Single-chip Mode - All address space is mapped within the MCU Expanded Mode - Address space is mapped both externally and within the MCU Mode features Max. addressability Max. # of modes 64Kbytes N/A 1 Single-chip Expanded H8/300L Single-chip Expanded H8/300 Single-chip Expanded H8/300H 16MB 52 Single-chip Expanded H8S 1MB 16MB 61 64KB 21

15 © 2008, Renesas Technology America, Inc., All Rights Reserved 15 Memory Maps External Address Space On-chip RAM External Area Internal I/O Registers External Area Internal I/O regs H’000000 H’FFB000 H’FFEFC0 H’FFF800 H’FFFF40 H’FFFF60 H’FFFFC0 On-chip RAM H’FFFFFF Addressing Modes 4 & 5 On-chip ROM On-chip RAM External Area Internal I/O Registers External Area Internal I/O regs H’000000 H’FFB000 H’FFEFC0 H’FFF800 H’FFFF40 H’FFFF60 H’FFFFC0 On-chip RAM H’FFFFFF External Address Space H’040000 Addressing Mode 6 On-chip ROM On-chip RAM Internal I/O Registers Internal I/O regs H’000000 H’FFB000 H’FFEFB0 H’FFEFBF H’FFFF3F H’FFFF60 H’FFFFC0 On-chip RAM H’FFFFFF H’03FFFF Addressing Mode 7

16 © 2008, Renesas Technology America, Inc., All Rights Reserved 16 Data Access Timing Access TypeBus Width (bits)Min. Cycle (state) On-chip memory161

17 © 2008, Renesas Technology America, Inc., All Rights Reserved 17 Accesses to Peripheral Registers 2222 8 16 On-chip peripherals Min. Cycle (state)Bus Width (bits)Access Type

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19 © 2008, Renesas Technology America, Inc., All Rights Reserved 19 Course Summary  H8S CPU architecture  Register set  Data format  Addressing modes  Instruction sets  Operating modes  Memory map  Accesses to memory, peripheral registers To get detailed information on H8S MCUs and the many other embedded system solutions from Renesas, go to: www.renesas.com Experiment with H8S MCUs and development tools in remotely controlled laboratory setups.


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