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Construction of Latency-Bounded Clock Trees Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh Purdue University.

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Presentation on theme: "Construction of Latency-Bounded Clock Trees Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh Purdue University."— Presentation transcript:

1 Construction of Latency-Bounded Clock Trees Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh Purdue University

2 On-Chip Variations 175 ps225 ps i j 75 ps125 ps Process variations Voltage variations Temperature variations

3 Outline Motivation Problem Formulation Proposed Latency Constraint Graph (LCG) Proposed Tree Construction Framework Experimental Results and Future Work

4 Skew Constraints Combinational Logic FF i FF j Setup time: Hold time: DDD

5 Clock Tree Synthesis Objective: Connect source to sinks – Buffers – Wires Constraints: – Transition time – Skew D Q Clock Source Clock Sinks a b c d wire buffer

6 Clock Tree Synthesis

7

8 On-Chip Variations D Q Clock Sinks a b c d CCA(a,b) CCA(b,c) Estimate OCV Delay variations by OCV and Safety margin

9 Problem Formulation (1) Estimate and. (2) Construct clock trees with and. Construct a clock tree with and !

10 -30 = = 40 -20 = = 10 SCG and Safety Margins D Q a b c d Find: a b c d 30 10 40 20 -10 20 30 10 0 With Safety Margin to OCV

11 20 30 Greedy-UST/DME D Q a b c d Source FSR ab = [-d ab, d ba ] [17] C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. ACM TODAES, pages 359–379, 2002. a b d c 10 0 -5 5

12 Construction of Latency-Bounded Clock Trees 175 ps225 ps D Q i j 75 ps125 ps

13 Latency a b c 5 20 40 a b c 65 40 55 The latency is dependent on the subtree latencies and the skew constraints

14 Proposed Latency Constraint Graph (LCG) abc 50 60 -10 -15 Latency Path SCG -5 -20 -40 Virtual sink Virtual source 0 0 0 LCG (negative) Bottom-up shortest path to vertex i: =[65, 55, 40] - (0 +(-10) +(-15)+(-40) = 65 -5 -20 -40 0 0 0 [65, 55, 40]

15 Root Construction a b c 5 20 40 c a b 65 40 55 5 20 40 LCG 6035 0 Compute delay insertions Minimum latency and maximal sharing of delay insertions

16 Root Construction Sort based on Topology selection Inexact Delay Realization a b c 65 40 55 5 20 40 25 35 0 Maximal sharing of delay insertions 25 c a b 65 40 55 5 20 40 6035 0

17 Tree Construction Delay insertions Skew commitments abc 60 -20 Virtual source 0 0 0 -5-40 Delay insertion Skew commitment -(40 +X ) -10 50 -a a -15 Delay insertion

18 Latency-Bounded Tree Construction abc 50 60 -10 -15 -20 -40 Virtual source Virtual sink 0 0 0 Feasible latency range -5 FLSR FSR FLR a b 5 20 40 c

19 Virtual latency Root location abc 50 60 -10 -15 -20 Virtual source Virtual sink 0 0 0 -5 Virtual latency = d root * c delay 30 -40 -(40 + 30)

20 Flow CTS CTO Input Output Merging Buffer insertion Input to CTS Output from CTS Subtree dragging Latency Aware Merging Latency locking Update of virtual latency Root construction

21 Experimental Setup Arbitrary skew constraints Monte Carlo Framework with on-chip variations – Process variations – Voltage variations – Temperature variations NameSinksSkew constraints scaled_s15850597318 ecg767463440 aes1321653382 [14] C. N. Sze. 2010. ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD’10.

22 Various Safety Margins on ecg Before CTOAfter CTO Circu it Struc- ture M user Lat- ency (ps) Cap (pF) TNS (ps) WNS (ps) Yield (%) TNS (ps) WNS (ps) Yield (%) ecgTree in [8]2042057-4577-2482.6-9342-460.0 Tree2034432-7061-2492.8-9443-3123.2 R-Tree2031730-1983-1675.6-3085-1863.0 ecgTree in [8]3041767-1569-1998.8-1874-2091.6 Tree3045440-2849-2197.4-4122-3786.0 R-Tree3038235-205-699.4-24-399.4 ecgTree in [8]4071696-245-1596.2-158-1098.6 Tree4085062-1890-1899.6-2140-2699.0 R-Tree4081158-419-1694.2-3-299.8 [8] R. Ewetz and C-K. Koh. 2015. A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD’15

23 Latency-Bounded Clock Trees Before CTOAfter CTO Circ uit Struc- ture M user (ps) L user (ps) Lat- ency (ps) Cap (pF) TNS (ps) WNS (ps) Yield (%) TNS (ps) WNS (ps) Yield (%) s15R-Tree25∞30317.3-291-3080.4-182-2081.4 850L-R-Tree2527024817.7-96-1599.2-45-6100.0 L-R-Tree2525021418.3-78-10100.0-30-7100.0 ecgR-Tree30∞38235.8-205-699.4-24-399.4 L-R-Tree3038031835.0-345-1694.6-4100.0 L-R-Tree3036032539.1-823-1299.8-260-10100.0 aesR-Tree50∞2207208-2877-2782.8-13-397.6 L-R-Tree5020001863234-1492-18100.0-13-299.0 L-R-Tree5018001638234-2064-29100.0-119-498.2

24 Summary and Future Work Proposed a latency constraint graph Tree construction based on the LCG Estimate and. Questions?

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