1. W4118 Operating Systems Instructor: Junfeng Yang

2. Logistics  Homework 4 due 3:09pm 3/26 1

3. Last Lecture: Memory Management  Dynamic memory allocation  Stack: last in first out  Heap: allocate from random locations  Fragmentation  Memory allocation strategy: best fit, first fit, worst fit  Intro to Memory management  Multiprogramming wishlist: Sharing, Transparency, Protection, Efficiency  Transparency  relocation Process can run anywhere in memory  When? 2

4. Last lecture: Relocation at Execution Time  Map program-generated address to hardware address dynamically at every reference  MMU: Memory Management Unit Controlled by OS  Program: logical (virtual) address  Hardware: physical (real) addresses  Address space: each process’s view of memory 3 CPUMMU MEMORY Logical Addresses Physical Addresses

5. Last lecture: Implementation  Translation on every memory access  Compare logical address to limit register If greater, generate exception  Add base register to logical address to generate physical address 4 CPU base limit <= limit? + Logical Addresses Physical Addresses exception no

6. Last lecture: Pros and Cons of Base and Limit  Continuous allocation: each process is in a contiguous memory block  Advantages  Supports dynamic relocation of address space  Supports protection across multiple spaces  Cheap: few registers and little logic  Fast: add and compare can be done in parallel  Disadvantages  Each process must be allocated contiguously in real memory External Fragmentation: cannot allocate a new process  Must allocate memory that may not be used  No sharing: cannot share limited parts of address space e.g. cannot shared code with private data 5

7. Today: Paging  Goal  Eliminate external fragmentation  Don’t allocate memory that will not be used  Enable sharing  Idea: Divide memory into fixed-sized pages  Both virtual and physical memory are composed of pages  Book call virtual page page, physical page frame

8. Implementing paging  Keep track of all free physical page frames  To run a program of size n pages, need to find n free frames and load program  Pages do not need to be contiguous!  Set up mapping from virtual to physical in page table  At memory reference time, translate virtual address to physical address using page table

9. Address Translation Scheme  Address generated by CPU is divided into:  Page number (p) – used as an index into a page table which contains base address of each page in physical memory  Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit  For given logical address space 2 m and page size 2 n page number page offset p d m - n n

10. Paging Hardware

11. Paging Model of Logical and Physical Memory

12. Free Frames Before allocation After allocation

13. Where Are Page Tables Stored?  Page tables can be large  32 bit address space, 4K page  2^20 pages  Assume 4 bytes for each page table entry  4 MB for page table !  Page table is stored in main memory  Page-table base register (PTBR) points to page table in memory  Each process PCB has a copy of its PTBR points to its page table  Context switch code must switch PTBR  Problem: each data/instruction access requires two memory accesses  One for the page table and one for the data/instruction.

14. Reduce # of Memory References  The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)  TLB is fast (CPU speed), but small

15. TLB  Parallel search Address translation (p, d)  If p is in associative register, get frame # out  Otherwise get frame # from page table in memory Virtual Page #Physical Page #

16. Paging Hardware With TLB

17. Effective Access Time  Associative Lookup =  time unit  Assume memory cycle time is 1 microsecond  Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers  Hit ratio =   Effective Access Time (EAT) EAT = (1 +  )  + (2 +  )(1 –  ) =  +  + 2 +  -  - 2  = 2 +  – 

18. TLB Miss  Can be handled in hardware and software  Hardware (CISC: x86)  Pros: hardware doesn’t have to trust OS !  Cons: complexity  Software (RISC: MIPS, SPARC)  Pros: flexibility  Cons: code may have bug  Question: what can’t a TLB miss handler do? 17

19. TLB sharing  What happens to TLB on context switches?  How to share TLB entries between two processes?  ASID: Address Space Identifier 18

20. Memory Protection  Memory protection implemented by associating protection bit with each frame  Valid-invalid bit attached to each entry in the page table:  “ valid ” indicates that the associated page is in the process ’ logical address space, and is thus a legal page  “ invalid ” indicates that the page is not in the process ’ logical address space  Can have read, write, execute protection as well  These bits exist in TLB entries as well

21. Valid (v) or Invalid (i) Bit In A Page Table

22. Shared Pages  Shared code  One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems).  Shared code must appear in same location in the logical address space of all processes  Private code and data  Each process keeps a separate copy of the code and data  The pages for the private code and data can appear anywhere in the logical address space

23. Shared Pages Example

24. Page Table Size Issues  Given:  A 32 bit address space (4 GB)  4 KB pages  A page table entry of 4 bytes  Implication:  Page table is 4 MB per process!  Huge size and context switching costs  Address space usage tends to be sparse  Most programs don ’ t use all of 32 bits

25. Structure of the Page Table  Hierarchical Paging  Hashed Page Tables  Inverted Page Tables

26.  Break up the logical address space into multiple page tables  A simple technique is a two-level page table Hierarchical Page Tables

27. Two-Level Paging Example  A logical address (on 32-bit machine with 1K page size) is divided into:  a page number consisting of 22 bits  a page offset consisting of 10 bits  Since the page table is paged, the page number is further divided into:  a 12-bit page number  a 10-bit page offset  Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page number page offset pipi p2p2 d 12 10

28. Address-Translation Scheme

29. Three-level Paging Scheme

30. Hashed Page Tables  Common in address spaces > 32 bits  The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.  Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

31. Hashed Page Table

32. Inverted Page Table  One entry for each real page of memory  Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page  Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs  Use hash table to limit the search to one — or at most a few — page-table entries

33. Inverted Page Table Architecture

34. Backup Slides

35. Segmentation  Memory-management scheme that supports user view of memory  A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

36. User ’ s View of a Program

37. Logical View of Segmentation 1 3 2 4 1 4 2 3 user spacephysical memory space

38. Segmentation Architecture  Logical address consists of a two tuple:,  Segment table – maps two-dimensional physical addresses; each table entry has:  base – contains the starting physical address where the segments reside in memory  limit – specifies the length of the segment  Segment-table base register (STBR) points to the segment table ’ s location in memory  Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR

39. Segmentation Architecture (Cont.)  Protection  With each entry in segment table associate: validation bit = 0  illegal segment read/write/execute privileges  Protection bits associated with segments; code sharing occurs at segment level  Since segments vary in length, memory allocation is a dynamic storage-allocation problem  A segmentation example is shown in the following diagram

40. Segmentation Hardware

41. Example of Segmentation

42. Example: The Intel Pentium  Supports both segmentation and segmentation with paging  CPU generates logical address  Given to segmentation unit Which produces linear addresses  Linear address given to paging unit Which generates physical address in main memory Paging units form equivalent of MMU

43. Logical to Physical Address Translation in Pentium

44. Intel Pentium Segmentation

45. Pentium Paging Architecture

46. Linear Address in Linux Broken into four parts:

47. Three-level Paging in Linux

48. Paging in 64 bit Linux Platform Page Size Address Bits Used Paging Levels Address Splitting Alpha8 KB43310+10+10+13 IA644 KB3939+9+9+12 PPC644 KB41310+10+9+12 sh644 KB41310+10+9+12 X86_644 KB4849+9+9+9+12