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Multiple Scattering and Sensor Thickness Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical.

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Presentation on theme: "Multiple Scattering and Sensor Thickness Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical."— Presentation transcript:

1 Multiple Scattering and Sensor Thickness Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical support: Sensor Thickness  m amam bmbm 253.5 8.9 503.7 9.6 1253.811.7 3004.017.5 Mokka+Marlin Simulation of VXD02  need thin monolithic pixel sensor. e + e -  HZ  bb  +  - at 0.5 TeV

2 CMOS Sensor Back-thinning Back-thinning of diced CMOS chips by partner Bay Area company: Aptek. Aptek uses grinding and proprietary hot wax formula for mounting die on grinding plate: Chip mounted on PCB with reversible glue and characterized Chip removed from PCB Back-thinningChip re-mounted and re-characterized Backthinning yield ~ 90 %, chip thickness measured at LBNL after processing: “50  m” =  m, “40  m” =  m; three chips fully characterised: Thin sensitive epi-layer makes CMOS Pixel sensors in principle ideally suited for back-thinning w/o significant degradation of performance expected (especially S/N), but questions arise from earlier results; SEM Image of CMOS Pixel Chip Bulk Si Epi Si SiO + Metal

3 40  m  Back-thinned Sensor Tests Study change in charge collection and signal-to-noise before and after back-thinning: Mimosa 5 sensors (IPHC Strasbourg), 1 M pixels 17  m pitch, 1.8 x 1.8 cm 2 surface 55 Fe Determine chip gain and S/N for 5.9 keV X rays Collimated Laser Compare charge collection in Si at different depths 1.5 GeV e - beam Determine S/N and cluster size for m.i.p. S/N CMOS sensors back-thinning feasible NIM A579 (2007) 675

4 Definition of overall material budget rescaled from VXD3 SLD VXD3 ILC VTX Beampipe liner Ti 50  m 0.14%Ti 25  m 0.07% Beampipe Be 760  m 0.22%Be 400  m 0.14% Inner gas shell Be 560  m 0.16% 0 Ladder/layer 0.41% 0.11% Outer gas shellBe mesh 0.48% 0.28% Cold N2 Gas 0.05% Cryostat coating Al 500  m 0.58% 0.22% Cryostat foamUrethane 0.44%NilFlam 0.12% Extrapolation from experience at SLD VXD3 to STAR HFT Su Dong/SiD

5 STAR HFT Ladder Program of engineering design, construction and characterization of full ladder equipped with back-thinned CMOS pixel sensors based on experience from STAR HFT project and in collaboration with them; 0.282% X 0 STAR Low mass carrier: 50  m CFC+3.2mm RVC+50  m CFC (=0.11%X 0 ); ComponentThickness (% X 0 ) Pixel Chip0.054 Adhesive0.014 Kapton Cable0.090 Adhesive0.014 Carrier0.110 Total0.282

6 STAR HFT Cable ~ 100 traces (2 LVDS pairs / sensor, clk, power, gnd, cntl ) 4 layer design, 25 µm kapton, 20 µm Al conductor Impedance controlled signal / clock pairs with power and ground geometrically arranged as shielding. L Greiner, Snowmass 2005

7 STAR HFT Ladder Testing Mechanical and thermal characterization of STAR prototype, study of heat removal using low-speed airflow; IR Camera Image Air Cooling Test Thin ChipsHeating cable (80mW/cm 2 ) T( 0 C) r.m.s displacement on unsupported end of ladder mounted at one end, w/ quasi-laminar airflow at 20 o angle STAR Prototype Capacitive Probe Measurement

8 STAR HFT Ladder Testing STAR study of accuracy of chip positioning on carrier: 50  m back-thinned MIMOSA5 are positioned using a vacuum chuck with alignment bump edge and individual vacuum chuck valves; Profile of Chip Elevation on CarrierChip Corner Locations Flat to ~ 30  m Accurate to ~ 20  m Measurements using Optical Survey Machine with ~ 1  m accuracy.

9 VTX Ladder Design & Testing Performed surveys of 40  m and 50  m thin chips and FEA analysis of stress on flattened chip, results suggest sandwich ladder design; FEA stress analysis of flattened 50  m chip Measured Surface Map of 50  m thin chip 2 mm

10 VTX Ladder Design & Testing Performed surveys of 40  m and 50  m thin chips and FEA analysis of stress on flattened chip, results suggest sandwich ladder design;

11 VTX Ladder Design & Testing FEA of prototype sandwich structure: (core-cooled Si/CF/RVC sandwich, Si/Al/RVC sandwich); Core-cooled ladder concept is promising, optimisation in progress to move to prototyping in 2008; Low density (0.2-0.6 g/cc) high thermal conductivity (40-180 W/m K) foam Concept for Symmetric Ladder Sandwich Support with Air Cooling through Core Vertex Tracker Design with core-cooled ladders

12 Track Alignment of T966 Telescope


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