1. FE-I4 Architecture & Performance Marlon Barbero, Universität Bonn 2 nd ATLAS CMS Electronics for SLHC, CERN Mar. 04 th 2009

2. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 2 FE-I4 for IBL & sLHC IBL (~2014): inserted layer @ 3.7cm in current pixel detector. sLHC tentative layout (>2017): pixel layers at 3.7cm, 7.5cm, 16cm, 20cm (note: Discussion on boundary pixel / short strips, …). tentative ID layout for sLHC 2 layers long strips 3 layers short strips fixed removable 4 layers pixels IBL R~37 FE-I4 M. Garcia-Sciveres, ACES Mar. 03 rd 09

3. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 3 FE-I4: Some Specifications – Pixel size: 50×250μm 2. – Pixel array: 80 columns×336 rows = 26880 pixels/FE. – Dimensions FE-I4: ~ 20×19 mm 2. – Analog goals: 1.5V, 10μA/pixel. Digital goals: 1.2V, 10μA/pixel. – Analog information: ToT coded on 4 bits. – pseudo-LVDS output: 160Mb.s -1. – Rad.-hardness: >200MRad ionizing dose (FE-I3: >50Mrad). – Minimal guidelines: no ELT, nmos guard rings for analog & sensitive digital circuitry. – Sensor capacitance: 0-0.5pF. – Low noise at low cap. (~100e - ). – DC leakage I tolerant to Ileak > 100nA. A. Mekkaoui, ACES Mar. 04 th 09

4. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 4 Digital Readout Architecture FE-I3 bottleneck Both FE readout based on double column (DC) structure FE-I4 local storage All hit pixels are shipped to EoC buffer. A hit pixel need to transfer its data to EoC before accepting new hit  congestion. Each pixel is logically independent inside the DC. Store data locally in DC until L1T. Only 0.25% of pixel hits are shipped to EoC  DC bus traffic “low”. Warning: Local Buffer Congestion??? Each pixel tied to its neighbors -time info- (real hits clustered). TW out. low traffic on DC bus

5. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 5 Simulation Pile-up inefficiency: α (hit rate; mean(ToT); area).  untie neighbor pixels if needed & aggressive return to baseline. Local buffer overflow:  increase Logic Unit / Local Buffer Region (averaging out effect) & increase # of cells per Local Buffer. Two sources of inefficiencies are identified in the FE-I4 architecture #? ;; David Arutinov - Bonn LHC 0.13% 3xLHC 0.56% sLHC 1.9% Mean ToT = 4 n – true interaction rate m – recorded count rate τ - mean ToT n m = 1+n τ Simulation Analytical Pile-up inefficiency.

6. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 6 Local Buffer Overflow (2x2) Local Buffer Overflow Inefficiency for the 3.7cm layer 0.5% - 5 cells 0.01% ~ 7-8 cells 0.1% - 6 cells 3xLHC Latency 120 BX Latency (BX) x6 sLHC 3xLHC 120 BX SimulationAnalytical

7. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 7 Inefficiency FE-I4 2x2 Mean ToT = 4 0.6% x6 At 3 times LHC luminosity, r~3.7cm, FE-I4 inefficiencies should be in acceptable range

8. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 8 Towards a reference design DC 4 pixel region Now all pixels in buffer area are ‘semi’-tied together. Due to the smaller radius (3.7 cm vs. 5.05 cm) charge sharing in Z becomes comparable with r/phi. Memories SimulationAnalytical 3xLHC10xLHC3xLHC10xLHC 5 0.0472.190.0292.25 6 0.0110.650.0030.57 7 <0.010.16<0.010.13 η=0 η=2.5 n: buffer occupied. k: total # of buffer. ρ=λμ, with λ: hit probability. μ: busy time. Erland-B function pn=pn=

9. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 9 Region Schematic A 4-pixel unit with these functionalities: Time-Stamping (up to 5 stored at a time). ToT coded on 4 bits: no hit, small hit, long hit, analog values. Neighbor bit. Small hit  Available to Neighbor Region. disc. top left disc. bot. left disc. top right disc. bot. right 5 ToT memory /pixel 5 latency counter / region hit proc.: TS/sm/big/ToT Read & Trigger Neighbor Token L1TRead

10. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 10 Digital Column Architecture 168 regions + CLK + buffering scheme  1 Double-Column Simple buffer. H-tree. Delay compensated for skew balancing.

11. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 11 Work in progress 188  m 94  m 50  x8 delay matching - clk addresses region layout region symbol DC schem. drop on vdd Tomasz Hemperek - Bonn

12. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 12 FE-I4 Performance Inefficiency 3.7cm @ 3xLHC:  0.56% (double-hit) + 0.05% (5-deep buffer overflow). (  ~0.35%+~0.0065% for 16cm sLHC -50ns bx-) Area:  cells from provider, 100 x 102 um 2. Power:  1 hit/bx/DC, 100kHz L1T, 2.6uW / pixel. Warning: This is before adding any buffering, clock distribution…  5-6uW digital total?

13. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 13 Needs in Periphery Focus needs to shift to periphery. Command decoder  L1T / configuration. Ctrl block  handles token pass, read request to DC, readout from DC. Data Formatting  Data Output Protocol, compression, 8b10b. Data transmission  pseudo-LVDS output from fast CLK. Power blocks  regulator. Pad frame.

14. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 14 Status of FE-I4 Periphery Pix Array: data compression 80×336 pixel array data formatting (protocol) with error detection (parity/CRC?) ‘LVDS’-out 160Mb/s 2 monitoring config. Periphery: Asynch. FIFO PLL, 40MHz in, 160MHz out 40MHz ctrl block interface L1T global config DACs pixel config trigger FIFO Bypass-able EoC Powering clk select 160MHz aux L1T, token, read, … EoC token EoC token 28 b × 40 DC : in “advanced stage” : “effort needed”

15. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 15 Summary FE-I4 Architecture Lot of work performed during last 4-6 months on digital region + digital Double-Column.  will remain high in priority list in coming months (performance studies, improvements, optimization). Focus has started shifting to FE periphery.  Much effort needed there (interface, data output protocol, control block…). Validation, testability. Milestones 2009: Reviews foreseen for 2009, March and early summer. Full scale design completed: fall 2009. Needless to say, this is an aggressive schedule.

16. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 16 FE-I4_proto1 collaboration Participating institutes: Bonn, CPPM, Genova, LBNL, Nikhef. Bonn: D. Arutinov, M. Barbero, T. Hemperek, M. Karagounis. CPPM: D. Fougeron, M. Menouni. Genova: R. Beccherle, G. Darbo. LBNL: R. Ely, M. Garcia-Sciveres, D. Gnani, A. Mekkaoui. Nikhef: R. Kluit, J.D. Schipper FE-I4-P1 LDO Regulator Charge Pump Current Reference DACs Control Block Capacitance Measurement 3mm 4mm 61x14 array SEU test IC 4-LVDS Rx/Tx ShuLDO +trist LVDS/LDO/10b-DAC

17. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 17 backup BACKUP SLIDES

18. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 18 FE-I4 Originally developed as an IC for b-layer upgrade. Similar bandwidth for IBL and outer layers at sLHC ~2017 + schedule construction sLHC outer layers sooner than insertable inner layers  FE-I4 a good fit for both projects. FE-I4 for IBL requires: – hit rate ×4-5 wrt FE-I3, 5cm. – small pixel & big chip (active fraction). – compatible w. present RO & ctrl. – compatible w. different sensor types. FE-I4 for outer layers @ sLHC requires: – big chip for costs reduction. – compatible w. sLHC RO & ctrl. – lower current & compatible new powering schemes.

19. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 19 Motivation for re-design of FE Need for new FE: Smaller b-layer radius + potential luminosity increase  higher hit rate  FE-I3 column-drain architecture saturated.  FE-I4 has new digital architecture.  FE-I4 has smaller pixel (reduced cross-section). Enhancements brought to FE-I4: Improved active area ratio (<¾  0.9):  Bigger IC; reduced periphery; cost. Power:  Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. Adapt to sensor technologies with different cap. / leak. New technology:  Availability, rad-hard, higher integration density for digital circuits. 0.25μm  130nm FE-I3  FE-I4 Hit prob. / DC inefficiency LHC 3xLHC sLHC FE-I3 (5cm)

20. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 20 4-pixel / 8-pixel Local Buffer Overflow Inefficiency Quadri-pixel vs. Octo-pixel. Averaging out effect.

21. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 21 FE-I4 geometry 250 μm × 50 μm. Array: 80 columns × 336 rows. No bricking. 7.6mm 8mmactive 2.8mm 16.8mm 20.2mm ~2mm ~200 μ m FE-I3 74% FE-I4 ~89% Chartered reticule (24 x 32) IBM reticule vendor’s max chip size: 21mm×19.5mm (review when above 20mm) ~19 mm

22. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 22 Some target specs for FE-I4 Rad.-hardness: >200MRad ionizing dose (FE-I3: >50Mrad). Minimal guidelines: no ELT, nmos guard rings for analog & sensitive digital circuitry. Sensor capacitance: 0-0.5pF. Low noise at low cap. (~100e - ). DC leakage I tolerant to > 100nA. FE-I3FE-I4 Pixel Size [μm 2 ]50×40050×250 Pixel Array18×16080×336 Chip Size [mm 2 ]7.6×10.820.2×19.0 Active Fraction74%89% Analog Current [μA/pix]2610 Digital Current [μA/pix]1710 Analog Voltage [V]1.61.5 Digital Voltage [V]21.2 pseudo-LVDS out [Mb/s]40160

23. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 23 Clock Multiplier For IBL, need to transmit data out at BW of 160Mb/s 2 options: – send a 80MHz CLK to the FE and use both edges to transmit Needs modification of BOC / ROD to produce higher speed TTC Needs synchronization protocol on the FE between 80MHz clock & beam crossing. A new DORIC needs to decode CLK at twice frequency – send a 40MHz CLK to the FE and multiply clock on FE Needs a clock multiplier on chip Note: synergy with what the strip MCC need In FE-I4, we will provide both options: – Clock multiplier from the 40MHz input clock – AUX: possibility to send the 80MHz to the FE I/O choices for ATLAS IBL, ATLAS Pixel System Design Task Force

24. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 24 8b10b encoder For IBL, need to transmit data out at BW of 160Mb/s At BOC/ROD: – Data rate 4 times the clock rate – Phase adjustment Use Clock Data Recovery mechanism CDR requires an output data stream with good engineering properties 8b10b: – adequate for this purpose, enough transitions for reliable CDR – widely used  easy to implement – provides some level of error detection – provides comma for frame identification & synchronization I/O choices for ATLAS IBL, ATLAS Pixel System Design Task Force

25. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 25 PLL Overview Charge Pump Voltage Controlled Oscillator Phase Frequency Detector Frequency Divider Loop Filter Conversion and Buffering 40 MHz 640 MHz

26. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 26 Analog Readout Chain In FE-I4_proto1 (FE-I4 prototype submitted spring 2008): 2-stage architecture optimized for low power, low noise, fast rise time.  Additional gain, Cc/Cf2~6.  More flexibility on choice of Cf1.  Qcoll less dependant on Cdetect.  2 nd stage decoupled from leakage related DC potential shift. 12b configuration:  FDAC: tuning feedback current.  TDAC: tuning of discriminator threshold.  Local charge injection circuitry. Preamp Amp2 FDAC TDAC Config Logic discri 50  m 145  m

27. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 27 Irradiation in 2008 Sept. Los Alamos 800MeV p+  FE-I4-Proto1 FE, #1 (50Mrad) & #2 (100Mrad) ‏ Oct. CERN 20GeV p+  SEU test chip + LVDS test chip (used for interface and received a low parasitic dose ) Dec. Los Alamos 800Mev p+  FE-I4-Proto 1 chips #2 (an additional 100MRad) and #3 (200MRad) ‏  LVDS chips #1,#2 and #3,#4 Laser along beam line Beam stop FE-I4-proto1 LVDS RxTx

28. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 28 SEU-hardened latch CPPM has studied the influence of various layout of a DICE latch on the SEU x-section. Latch5.1 and latch5.2 ; Area :12µm × 4µm = 48 μm 2 nMos separation : 7µm ; pMos separation : 3 µm Physical separation of sensitive node pairs. Calin et al, IEEE Trans. Nucl. Sci. vol43, n.6, 1996 1.a 1.b 2.a 2.b 3.a 3.b 1.a 1.b 2.a 2.b 3.a 3.b Triple Redundant Logic with Interleaved Layout. X-section [cm 2.bit -1 ]: - Standard Latch: ~ 5.10 -14 - DICE w. improved layout: ~ 3.10 -16 X-section : < 1.10 -17

29. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 29 LVDS transciever For IBL and outer layers sLHC, need for a 320Mb.s -1 BW/ LVDS i/0. LVDS transciever IC irradiated up to ~180Mrad. No degradation observed. IBM 130nm 0.8mm 1.8mm 40MHz 160MHz 320MHz Clock-Rate Common Mode Voltage 1050mV 600mV 150mV TX output Chained RxTx output @ 320 MHz Clock tests with differential probe and 100 Ω on board term. @ 1.2V supply

30. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 30 Output Stage: PLL & 8b10b Compatibility w. current BOC / ROD. Clock multiplier from the 40MHz input clock – Classic PLL design: Phase Freq. Detector, Loop Filter, Voltage Controlled Oscill., Freq. Divider. – Phase Frequency Detector w. Upset Detection Unit. – Settling in 1.2μs; fast recovery from SEU in divider & Vctrl. 8b10b: – higher frequency clk & data  recover clk from data. – balanced coding for Clock Data Recovery in BOC / ROD. – some nice features (error detection, frame alignment). Both blocks by-passable for maximum flexibility. I/O choices for ATLAS IBL, ATLAS Pixel System Design Task Force

31. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 31 Out-Stage: tri-state pseudo-LVDS MUXing FE output for outer layers. M3-M6 steered by tri-state logic block  all switch can be left open  hZ. tri-state LVDS submitted. Testing is starting. DIENNNnPPnOut 000011hZ 100011 0101010 1110101 Tri-State logic

32. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 32 Others Note: – Low power comparator. – Failsafe mechanism of LVDS receiver. – Pad-frame. – LDO with new 0-cell. – ShuLDO. Zero is introduced in the open loop transfer function by a frequency dependent voltage controlled current source Less peaking of Vout in comparison with compensation by R ESR of Cout output. Talk M. Karagounis -ID Powering -Tue. 24 th 2009 Vin= 1.6V Vout= 1.2V  1.5V

33. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 33 MC events Events: (Pythia generator) – WH(120GeV); H  bb. – overlaid with: 24 / 75 / 240 / 400 events pileup. “LHC”/“3×LHC”/ “sLHC” (25ns / 50ns bx) Sensor: Un-irradiated planar sensor, 260μm width. Note: 3D simulation in progress Geometry: (Geant3 simulation package) – pixel size: FE-I3: 400×50μm 2 ; FE-I4: 250×50μm 2. – first: 4 barrels, 3.7 (FE-I4) & 5.05/8.85/12.25 cm radius FE-I3. – new: 6 barrels, 3.7/5.05/8.85/12.25/16/21 cm radius FE-I4. Threshold: first  3750e -. New  down to 1000e -. _ V. Kostyukhin -3D Si- Mon. 23 rd 2009

34. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 34 Foreword: Minimal Bias events FE-I4 for: - b-layer upgrade: luminosity? radius?  75 ev pile-up & 3.7cm. - s-LHC: lumi.? radius?  240/400 ev pile-up & outer layer. Extrapolation to LHC energy:  extrapolation @ 14TeV: uncertainty ~ 30%? (1 st years operation crucial to feedback simulation) / interaction at η=0

35. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 35 3×LHC / b-layer replacement 40 80 120 160 200 100 0 0200300400500 600 r [mm] z [mm] 37 50.5 88.5 122.5 6.306.466.035.855.916.466.11 2.552.562.542.552.642.652.64 1.411.241.26 1.371.341.33 12.1011.5312.0111.8511.7212.118.02 rates given in [pixel hits.bx -1 cm -2 ] FE-I3, 50μm×400μm. FE-I4 simul., 50μm×250μm. η=0.1η=0.2η=0.3η=0.4η=0.5η=0.6η=0.7η=0.8 η=0.9 η=1.0 η=1.2 η=1.5 η=2.0 η=2.5 η=3.0 η=3.5

36. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 36 10×LHC (25ns bx) / sLHC 40 80 120 160 200 100 0 0200300400500 600 r [mm] z [mm] 324 524 37/37 70 131 201 50.5 88.5 122.5 36.8935.7635.9736.4635.9433.2623.23 mean: 35 mean: 19.5 mean: 7.8 mean: 4.7 mean: 2.3 210 150 FE-I4, 50μm×250μm. FE-I4 simul., 50μm×250μm. FE-I4 Nigel, 50μm×250μm. FE-I4 sdtf 220908, 50×250μm 2. rates given in [pixel hits.bx -1 cm -2 ] η=0η=0.1η=0.2η=0.3η=0.4η=0.5η=0.6η=0.7η=0.8 η=0.9 η=1.0 η=1.2 η=1.5 η=2.0 η=2.5 η=3.0 η=3.5

37. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 37 10×LHC (50ns bx) / sLHC 40 80 120 160 200 100 0 0200300400500 600 r [mm] z [mm] 324 524 37/37 70 131 201 50.5 88.5 122.5 mean: 60 mean: 34 mean: 13.4 mean: 8.4 mean: 3.9 210 150 FE-I4, 50μm×250μm. FE-I4 simul., 50μm×250μm. FE-I4 Nigel, 50μm×250μm. FE-I4 sdtf 220908, 50×250μm 2. rates given in [pixel hits.bx -1 cm -2 ] η=0η=0.1η=0.2η=0.3η=0.4η=0.5η=0.6η=0.7η=0.8 η=0.9 η=1.0 η=1.2 η=1.5 η=2.0 η=2.5 η=3.0 η=3.5 55.1038.6759.1560.1260.0258.7461.18

38. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 38 Extrapolations to other radius Reasonable fit with: exp(1.34-0.57*R)+0.15-0.0053*R sLHC, 50ns bx / 400 events pileup Hits/mm 2 r [cm] Hits/mm 2 r [cm] sLHC, 25ns bx / 240 events pileup Reasonable fit with: exp(0.86-0.58*R)+0.088-0.0031*R sLHC (25ns)sLHC (50ns) Radius layer [mm][pix.bx -1.cm -2 ] 373560 50.519.534 7010.618.4 88.57.813.4 122.54.78.4 1314.78.3 1504.27.1 2012.54.4 2102.33.9

39. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 39 Pixel occupancy  Data bandwidth Pixel hit rate  FE output bandwidth: – # bits / pixel transmitted? » address 7+9 bits, analog info 4+2 bits  22b? » data output protocol? Reduce data output by taking into account clustered nature of real physics hits. NUMBER OF PIXELS FE-I4, central module, 21cm layer FE-I4, central module, 3.7cm layer 10xLHC FE-I4, central module, 3.7cm layer 3xLHC

40. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 40 Pixel occupancy  Data bandwidth Example 3: clustered data out with fixed format. compression factor (all at 3×LHC) 3.7cm (vs. 21cm), η=0 indiv pixels: 4.09 (0.25)×(7+9+4+2)= 1.00 (1.00)A.U. static 1×2: 3.45 (0.18)×(7+8+2×4+2)=0.96 (0.83) A.U. dynamic 1×2: 3.02 (0.15)×(7+9+2×4+2)= 0.87 (0.74) A.U. static 1×4: 2.86 (0.17)×(6+8+4×4+4)=1.08 (1.08) A.U. dyn. in-DC 1×4: 2.43 (0.15)×(6+9+4×4+4)= 0.95 (0.95) A.U. dynamic 1×4: 2.13 (0.14)×(7+9+4×4+4)= 0.85 (0.94) A.U. DC(×40) row (×336) column rowToT NL assumption: 100kHz L1T, 336×80 pixels FE-I4 Disclaimer: no header, trailer, DC-balancing, error correction… dyn. 1×4 better at small R? (larger η!) dyn. 1×2 at large R? 10 6.count.FE -1.s -1 preliminary For reference in backup slides: same at higher η

41. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 41 Pixel occupancy  Data bandwidth Example 3: clustered data out with fixed format. compression factor (all at 3×LHC) 3.7cm mod.4 (vs. 21cm mod.6), indiv pixels: 3.96 (0.26)×(7+9+4+2)= 1.00 (1.00)A.U. static 1×2: 3.38 (0.20)×(7+8+2×4+2)=0.97 (0.87) A.U. dynamic 1×2: 3.05 (0.18)×(7+9+2×4+2)= 0.91 (0.79) A.U. static 1×4: 2.28 (0.17)×(6+8+4×4+4)= 0.89 (1.01) A.U. dyn. in-DC 1×4: 2.00 (0.15)×(6+9+4×4+4)= 0.80 (0.91) A.U. dynamic 1×4: 1.88 (0.14)×(7+9+4×4+4)= 0.78 (0.85) A.U. DC(×40) row (×336) column rowToT NL assumption: 100kHz L1T, 336×80 pixels FE-I4 Disclaimer: no header, trailer, DC-balancing, error correction… dyn. 1×4 better at small R? (larger η!) dyn. 1×2 at large R? 10 6.count.FE -1.s -1 preliminary

42. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 42 Data BW for IBL @ 3.7cm Trigger rate100 kHz Interactions per crossing75 Sensor model260um planar, unirradiated Comparator threshold4000e Output format for analog data3.7cm: Single pixel / Fixed frame dynamic 2 pixel phi pairing Bits / pixels per analog output frame21 / 1 (single pix) ; 26 / 2 (analog-2) Output format for binary data3.7cm layer: Fixed frame dynamic 2 pixel phi pairing / Fixed frame dynamic 4 pixel group Bits / pixels per binary output frame20 / 2 (Bin-2) ; 24 / 4 (Bin-4) Encoding, parity, redundancy or headersNone Layercomp. firing per cm^2 per BX Required bandwidth per chip (Mb/s) 3.7cm12.0Analog: 85 3.7cm12.0Analog-2: 75 3.7cm12.0Bin-2: 57.7 3.7cm12.0Bin-4: 45.8

43. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 43 Data BW for sLHC Trigger rate100 kHz Interactions per crossing400 Sensor model260um planar, unirradiated Comparator threshold4000e Output format for analog dataFixed frame dynamic 2 pixel phi pairing Bits / pixels per analog output frame26 / 2 Output format for binary dataFixed frame dynamic 2 pixel phi pairing (L2, L3) Fixed frame dynamic 4 pixel group (L0, L1) Bits / pixels per binary output frame24 / 4 (L2, L3) ; 20 / 2 (L0, L1) Encoding, parity, redundancy or headersNone Design marginFactor of 2 Layercomp. firing per cm^2 per BX Required bandwidth per chip (Mb/s) (analog / binary) chips/ module 320Mb/s LVDS outputs / module (analog / binary) EOS card data volume (Gb/s) (analog / binary) FE-I4 chip data losses (*) % 060.0749 / 45413 / 212.0 / 7.3n/a + 0.05 118.4230 / 14043 / 25.5 / 3.4n/a + 0.02 26.675 / 5841 / 12.4 / 1.80.18 + 0.01 33.942 / 3241 / 12.7 / 2.10.10 + 0 disks80 max?412.9?0.1-0.2?

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45. Marlon Barbero, FE-I4 Architecture & Performance, 2 nd ACES, CERN, Mar. 04 th 2009 45

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