1. Computer Evolution and Performance

2. ENIAC - background Electronic Numerical Integrator And Computer Electronic Numerical Integrator And Computer Eckert and Mauchly Eckert and Mauchly University of Pennsylvania University of Pennsylvania Trajectory tables for weapons Trajectory tables for weapons Started 1943 Started 1943 Finished 1946 Finished 1946 Too late for war effort Too late for war effort Used until 1955 Used until 1955

3. 3 ENIAC - details

4. Decimal (not binary) Decimal (not binary) 20 accumulators of 10 digits 20 accumulators of 10 digits Programmed manually by switches Programmed manually by switches 18,000 vacuum tubes 18,000 vacuum tubes 30 tons 30 tons 15,000 square feet 15,000 square feet 140 kW power consumption 140 kW power consumption 5,000 additions per second 5,000 additions per second

5. von Neumann/Turing Stored Program concept Stored Program concept Main memory storing programs and data Main memory storing programs and data ALU operating on binary data ALU operating on binary data Control unit interpreting instructions from memory and executing Control unit interpreting instructions from memory and executing Input and output equipment operated by control unit Input and output equipment operated by control unit Princeton Institute for Advanced Studies Princeton Institute for Advanced Studies IAS IAS Completed 1952 Completed 1952

6. Structure of von Neumann machine

7. IAS - details 1000 x 40 bit words 1000 x 40 bit words Binary number Binary number 2 x 20 bit instructions 2 x 20 bit instructions Set of registers (storage in CPU) Set of registers (storage in CPU) Memory Buffer Register Memory Buffer Register Memory Address Register Memory Address Register Instruction Register Instruction Register Instruction Buffer Register Instruction Buffer Register Program Counter Program Counter Accumulator Accumulator Multiplier Quotient Multiplier Quotient

8. Structure of IAS – detail

9. Cont.. MBR – contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit. MAR – specifies the address in memory of the word to be written from or read into MBR. IR – contains 8-bit opcode instruction being executed. PC – contains the address of the next instruction AC and MQ – hold temporarily operands.

10. Commercial Computers 1947 - Eckert-Mauchly Computer Corporation 1947 - Eckert-Mauchly Computer Corporation UNIVAC I (Universal Automatic Computer) UNIVAC I (Universal Automatic Computer) US Bureau of Census 1950 calculations US Bureau of Census 1950 calculations Became part of Sperry-Rand Corporation Became part of Sperry-Rand Corporation Late 1950s - UNIVAC II Late 1950s - UNIVAC II Faster Faster More memory More memory

11. IBM Punched-card processing equipment Punched-card processing equipment 1953 - the 701 1953 - the 701 IBM’s first stored program computer IBM’s first stored program computer Scientific calculations Scientific calculations 1955 - the 702 1955 - the 702 Business applications Business applications Lead to 700/7000 series Lead to 700/7000 series

12. Transistors Replaced vacuum tubes Replaced vacuum tubes Smaller Smaller Cheaper Cheaper Less heat dissipation Less heat dissipation Solid State device Solid State device Made from Silicon (Sand) Made from Silicon (Sand) Invented 1947 at Bell Labs Invented 1947 at Bell Labs William Shockley et al. William Shockley et al.

13. Transistor Based Computers Second generation machines Second generation machines NCR & RCA produced small transistor machines NCR & RCA produced small transistor machines IBM 7000 IBM 7000 DEC - 1957 DEC - 1957 Produced PDP-1 Produced PDP-1

14. Microelectronics Literally - “small electronics” Literally - “small electronics” A computer is made up of gates, memory cells and interconnections A computer is made up of gates, memory cells and interconnections These can be manufactured on a semiconductor These can be manufactured on a semiconductor e.g. silicon wafer e.g. silicon wafer

15. Generations of Computer Vacuum tube - 1946-1957 Vacuum tube - 1946-1957 Transistor - 1958-1964 Transistor - 1958-1964 Small scale integration - 1965 on Small scale integration - 1965 on Up to 100 devices on a chip Up to 100 devices on a chip Medium scale integration - to 1971 Medium scale integration - to 1971 100-3,000 devices on a chip 100-3,000 devices on a chip Large scale integration - 1971-1977 Large scale integration - 1971-1977 3,000 - 100,000 devices on a chip 3,000 - 100,000 devices on a chip Very large scale integration - 1978 -1991 Very large scale integration - 1978 -1991 100,000 - 100,000,000 devices on a chip 100,000 - 100,000,000 devices on a chip Ultra large scale integration – 1991 - Ultra large scale integration – 1991 - Over 100,000,000 devices on a chip Over 100,000,000 devices on a chip

16. Moore’s Law Increased density of components on chip Increased density of components on chip Gordon Moore – co-founder of Intel Gordon Moore – co-founder of Intel Number of transistors on a chip will double every year Number of transistors on a chip will double every year Since 1970’s development has slowed a little Since 1970’s development has slowed a little Number of transistors doubles every 18 months Number of transistors doubles every 18 months Cost of a chip has remained almost unchanged Cost of a chip has remained almost unchanged Higher packing density means shorter electrical paths, giving higher performance Higher packing density means shorter electrical paths, giving higher performance Smaller size gives increased flexibility Smaller size gives increased flexibility Reduced power and cooling requirements Reduced power and cooling requirements Fewer interconnections increases reliability Fewer interconnections increases reliability

17. Growth in CPU Transistor Count

18. IBM 360 System 360 is the industry’s first planned family of computers. The model are compatible in the sense that a program written for one model should be capable of being executed by another model in the series (diff only in time) System 360 is the industry’s first planned family of computers. The model are compatible in the sense that a program written for one model should be capable of being executed by another model in the series (diff only in time) The characteristics of a family are as follows: The characteristics of a family are as follows: Similar instruction set  In many cases, the exact same set of machine instructions is supported on all members of the family. Thus a program that executes on one machine will also execute on any other. Similar instruction set  In many cases, the exact same set of machine instructions is supported on all members of the family. Thus a program that executes on one machine will also execute on any other. Similar operating system  The same basic operating system is available for all family members. Similar operating system  The same basic operating system is available for all family members. Increasing speed  The rate of instruction execution increase in going from lower to higher family members. Increasing speed  The rate of instruction execution increase in going from lower to higher family members.

19. Cont.. Increasing I/O port  In going from lower to higher family members. Increasing I/O port  In going from lower to higher family members. Increasing memory  In going from lower to higher family members. Increasing memory  In going from lower to higher family members. Increasing cost  In going from lower to higher family members. Increasing cost  In going from lower to higher family members.

20. DEC PDP-8 1964 1964 First minicomputer. First minicomputer. Did not need air conditioned room Did not need air conditioned room Small enough to sit on a lab bench Small enough to sit on a lab bench Cheap $16,000, IBM360 $100k. Cheap $16,000, IBM360 $100k. Embedded applications & OEM Embedded applications & OEM Use BUS STRUCTURE- Omnibus Use BUS STRUCTURE- Omnibus

21. DEC - PDP-8 Bus Structure Omnibus consists of 96 separate signal paths, used to carry control, address, and data signals. Because all system components share a common set of signal paths, their use must be controlled by the CPU.

22. Semiconductor Memory In 1950s and 1960s, most computer memory was constructed from tiny rings of ferromagnetic material. In 1950s and 1960s, most computer memory was constructed from tiny rings of ferromagnetic material. In 1970, Fairchild produced the first relatively capacious semiconductor memory. In 1970, Fairchild produced the first relatively capacious semiconductor memory. Size of a single core Size of a single core i.e. 1 bit of magnetic core storage i.e. 1 bit of magnetic core storage Holds 256 bits of memory Holds 256 bits of memory Non-destructive read Non-destructive read Much faster than core Much faster than core Capacity approximately doubles each year Capacity approximately doubles each year

23. Intel 1971 – Intel developed 4004 1971 – Intel developed 4004 First microprocessor First microprocessor Contain all CPU components on a single chip Contain all CPU components on a single chip 4 bit 4 bit Followed in 1972 by 8008 Followed in 1972 by 8008 8 bit 8 bit 4004, 8008 designed for specific applications 4004, 8008 designed for specific applications 1974 - 8080 1974 - 8080 Intel’s first general purpose microprocessor Intel’s first general purpose microprocessor

24. Speeding it up Pipelining Pipelining On board cache On board cache On board L1 & L2 cache On board L1 & L2 cache Branch prediction – the processor looks ahead in the instruction code fetched from memory and predicts which branches, or group of instructions to be process next. Branch prediction – the processor looks ahead in the instruction code fetched from memory and predicts which branches, or group of instructions to be process next. Data flow analysis – the processor analyzes which instructions are dependent on each other’s result, or data, to create an optimized schedule of instructions. Data flow analysis – the processor analyzes which instructions are dependent on each other’s result, or data, to create an optimized schedule of instructions. Speculative execution – using branch prediction and data flow analysis, some processor speculatively execute instructions ahead of their actual appearance in the program execution, holding the results in temporary locations. This enables the processor to keep its execution engines as busy as possible by executing instruction that are likely to be needed. Speculative execution – using branch prediction and data flow analysis, some processor speculatively execute instructions ahead of their actual appearance in the program execution, holding the results in temporary locations. This enables the processor to keep its execution engines as busy as possible by executing instruction that are likely to be needed.

25. Performance Balance Processor speed increased Processor speed increased Memory capacity increased Memory capacity increased Memory speed lags behind processor speed Memory speed lags behind processor speed

26. Logic and Memory Performance Gap

27. Solutions Increase the number of bits that are retrieved at one time by making DRAMs “wider” rather than “deeper” and by using wide bus data paths. Increase the number of bits that are retrieved at one time by making DRAMs “wider” rather than “deeper” and by using wide bus data paths. Change the DRAM interface to make it more efficient by including a cache or other buffering scheme on the DRAM. Change the DRAM interface to make it more efficient by including a cache or other buffering scheme on the DRAM. Reduce the frequency of memory access by incorporating increasingly complex and efficient cache structures between the processor and main memory. Incorporation of one or more caches on the processor chip. Reduce the frequency of memory access by incorporating increasingly complex and efficient cache structures between the processor and main memory. Incorporation of one or more caches on the processor chip. Increase the interconnect bandwidth between processors and memory by using higher-speed buses and using hierarchy of buses to buffer and structure data flow. Increase the interconnect bandwidth between processors and memory by using higher-speed buses and using hierarchy of buses to buffer and structure data flow.

28. I/O Devices Peripherals with intensive I/O demands Peripherals with intensive I/O demands Large data throughput demands Large data throughput demands Processors can handle this Processors can handle this Problem moving data Problem moving data Solutions: Solutions: Caching Caching Buffering Buffering Higher-speed interconnection buses Higher-speed interconnection buses More elaborate bus structures More elaborate bus structures Multiple-processor configurations Multiple-processor configurations

29. Typical I/O Device Data Rates

30. Key is Balance Processor components Processor components Main memory Main memory I/O devices I/O devices Interconnection structures Interconnection structures

31. Improvements in Chip Organization and Architecture Increase hardware speed of processor Increase hardware speed of processor Fundamentally due to shrinking logic gate size Fundamentally due to shrinking logic gate size More gates, packed more tightly, increasing clock rate More gates, packed more tightly, increasing clock rate Propagation time for signals reduced Propagation time for signals reduced Increase size and speed of caches Increase size and speed of caches Dedicating part of processor chip Dedicating part of processor chip Cache access times drop significantly Cache access times drop significantly Change processor organization and architecture Change processor organization and architecture Increase effective speed of execution Increase effective speed of execution Parallelism Parallelism

32. Problems with Clock Speed and Login Density Power Power Power density increases with density of logic and clock speed Power density increases with density of logic and clock speed Dissipating heat Dissipating heat RC delay RC delay Speed at which electrons flow limited by resistance and capacitance of metal wires connecting them Speed at which electrons flow limited by resistance and capacitance of metal wires connecting them Delay increases as RC product increases Delay increases as RC product increases Wire interconnects thinner, increasing resistance Wire interconnects thinner, increasing resistance Wires closer together, increasing capacitance Wires closer together, increasing capacitance Memory latency Memory latency Memory speeds lag processor speeds Memory speeds lag processor speeds Solution: Solution: More emphasis on organizational and architectural approaches More emphasis on organizational and architectural approaches

33. Intel Microprocessor Performance

34. Increased Cache Capacity Typically two or three levels of cache between processor and main memory Typically two or three levels of cache between processor and main memory Chip density increased Chip density increased More cache memory on chip More cache memory on chip Faster cache access Faster cache access Pentium chip devoted about 10% of chip area to cache Pentium chip devoted about 10% of chip area to cache Pentium 4 devotes about 50% Pentium 4 devotes about 50%

35. More Complex Execution Logic Enable parallel execution of instructions Enable parallel execution of instructions Pipeline works like assembly line Pipeline works like assembly line Different stages of execution of different instructions at same time along pipeline Different stages of execution of different instructions at same time along pipeline Superscalar allows multiple pipelines within single processor Superscalar allows multiple pipelines within single processor Instructions that do not depend on one another can be executed in parallel Instructions that do not depend on one another can be executed in parallel

36. Diminishing Returns Internal organization of processors complex Internal organization of processors complex Can get a great deal of parallelism Can get a great deal of parallelism Further significant increases likely to be relatively modest Further significant increases likely to be relatively modest Benefits from cache are reaching limit Benefits from cache are reaching limit Increasing clock rate runs into power dissipation problem Increasing clock rate runs into power dissipation problem Some fundamental physical limits are being reached Some fundamental physical limits are being reached

37. New Approach – Multiple Cores Multiple processors on single chip Multiple processors on single chip Large shared cache Large shared cache Within a processor, increase in performance proportional to square root of increase in complexity Within a processor, increase in performance proportional to square root of increase in complexity If software can use multiple processors, doubling number of processors almost doubles performance If software can use multiple processors, doubling number of processors almost doubles performance So, use two simpler processors on the chip rather than one more complex processor So, use two simpler processors on the chip rather than one more complex processor With two processors, larger caches are justified With two processors, larger caches are justified Power consumption of memory logic less than processing logic Power consumption of memory logic less than processing logic Example: IBM POWER4 Example: IBM POWER4 Two cores based on PowerPC Two cores based on PowerPC

38. POWER4 Chip Organization

39. Pentium Evolution (1) 8080 8080 first general purpose microprocessor first general purpose microprocessor 8 bit data path 8 bit data path Used in first personal computer – Altair Used in first personal computer – Altair 8086 8086 much more powerful much more powerful 16 bit 16 bit instruction cache, prefetch few instructions instruction cache, prefetch few instructions 8088 (8 bit external bus) used in first IBM PC 8088 (8 bit external bus) used in first IBM PC 80286 80286 16 Mbyte memory addressable 16 Mbyte memory addressable up from 1Mb up from 1Mb 80386 80386 32 bit 32 bit Support for multitasking Support for multitasking

40. Pentium Evolution (2) 80486 80486 sophisticated powerful cache and instruction pipelining sophisticated powerful cache and instruction pipelining built in maths co-processor built in maths co-processor Pentium Pentium Superscalar Superscalar Multiple instructions executed in parallel Multiple instructions executed in parallel Pentium Pro Pentium Pro Increased superscalar organization Increased superscalar organization Aggressive register renaming Aggressive register renaming branch prediction branch prediction data flow analysis data flow analysis speculative execution speculative execution

41. Pentium Evolution (3) Pentium II Pentium II MMX technology MMX technology graphics, video & audio processing graphics, video & audio processing Pentium III Pentium III Additional floating point instructions for 3D graphics Additional floating point instructions for 3D graphics Pentium 4 Pentium 4 Note Arabic rather than Roman numerals Note Arabic rather than Roman numerals Further floating point and multimedia enhancements Further floating point and multimedia enhancements Itanium Itanium 64 bit 64 bit see chapter 15 see chapter 15 Itanium 2 Itanium 2 Hardware enhancements to increase speed Hardware enhancements to increase speed

42. PowerPC 1975, 801 minicomputer project (IBM) RISC 1975, 801 minicomputer project (IBM) RISC Berkeley RISC I processor Berkeley RISC I processor 1986, IBM commercial RISC workstation product, RT PC. 1986, IBM commercial RISC workstation product, RT PC. Not commercial success Not commercial success Many rivals with comparable or better performance Many rivals with comparable or better performance 1990, IBM RISC System/6000 1990, IBM RISC System/6000 RISC-like superscalar machine RISC-like superscalar machine POWER architecture POWER architecture IBM alliance with Motorola (68000 microprocessors), and Apple, (used 68000 in Macintosh) IBM alliance with Motorola (68000 microprocessors), and Apple, (used 68000 in Macintosh) Result is PowerPC architecture Result is PowerPC architecture Derived from the POWER architecture Derived from the POWER architecture Superscalar RISC Superscalar RISC Apple Macintosh Apple Macintosh Embedded chip applications Embedded chip applications

43. PowerPC Family (1) 601: 601: Quickly to market. 32-bit machine Quickly to market. 32-bit machine 603: 603: Low-end desktop and portable Low-end desktop and portable 32-bit 32-bit Comparable performance with 601 Comparable performance with 601 Lower cost and more efficient implementation Lower cost and more efficient implementation 604: 604: Desktop and low-end servers Desktop and low-end servers 32-bit machine 32-bit machine Much more advanced superscalar design Much more advanced superscalar design Greater performance Greater performance 620: 620: High-end servers High-end servers 64-bit architecture 64-bit architecture

44. PowerPC Family (2) 740/750: 740/750: Also known as G3 Also known as G3 Two levels of cache on chip Two levels of cache on chip G4: G4: Increases parallelism and internal speed Increases parallelism and internal speed G5: G5: Improvements in parallelism and internal speed Improvements in parallelism and internal speed 64-bit organization 64-bit organization

45. 45 Summary Computer Architecture includes the design of the Instruction Set Architecture (progammer’s view) and the Machine Organization (logic designer’s view). Computer Architecture includes the design of the Instruction Set Architecture (progammer’s view) and the Machine Organization (logic designer’s view). All modern computers use the stored program concept based on Von-neumann machine. All modern computers use the stored program concept based on Von-neumann machine. The 3 major components of a computer are The 3 major components of a computer are processor (CPU) processor (CPU) storage(memory) and storage(memory) and communication devices(input and output). communication devices(input and output). These 3 major components are interconnected through a system bus. These 3 major components are interconnected through a system bus.