1. DS-UWB FEC Decoder Design VLSI 자동설계연구실 정재헌

2. Topics on Communication Modem Design VLSI Design Automation LAB2  Outline  Top level block diagram  BM processor  ACS processor  Register-Exchange Window  Controller  Running Example  Performance and Results  Reference

3. Topics on Communication Modem Design VLSI Design Automation LAB3  Top level block diagram  Codeword is 3bit quantized.  K is 0 or 1, 0 means K=4, 1 means K=6.  Start signal is a pulse that provided with first codeword.  Dec_len signal is 16bit signal, means packet length.  Use active low reset.  Out_en signal is 1 when dout is decoded data.

4. Topics on Communication Modem Design VLSI Design Automation LAB4  BM processor  BM0 = BMI0 + BMI1  BM1 = BMI0 + not BMI1  BM2 = not BMI0 + BMI1  BM3 = not BMI0 + not BMI1  Input is 3bit, calculated output is 4bit.

5. Topics on Communication Modem Design VLSI Design Automation LAB5  ACS processor  Consist of butterfly module, nomalizer, path metric register(pm_reg)  Module sharing for K=4 and K=6, so butterfly module 0 to 3 input is multiplexed by K.  Because of feedback, pipelining is impossible.  Normalizer check MSB of butterfly output, if all is 1 then convert MSB to 0.

6. Topics on Communication Modem Design VLSI Design Automation LAB6  ACS processor  Butterfly module calculate path metric and branch metric, and select minimum path metric, and output path metric and survivor path pointer to update path metric and decode.  if pm0+bm0<pm1+bm1, spp0=0, pmo0=pm0+bm0, else spp0=1, pmo0=pm1+bm1  if pm0+bm1<pm1+bm0, spp1=0, pmo1=pm0+bm1, else spp1=1, pmo1=pm1+bm0  Each butterfly module input are in table below. pm_in0pm_in1bm_in0bm_in1 K-010101 bf0pm_out0pm_out4pm_out16bm0bm3 bf1pm_out1pm_out5pm_out17bm3bm2bm0bm1 bf2pm_out2pm_out6pm_out18bm1bm2 bf3pm_out3pm_out7pm_out19bm2bm1bm3bm0 bf4pm_out4pm_out20bm3bm0... bf15pm_out15pm_out31bm1bm2

7. Topics on Communication Modem Design VLSI Design Automation LAB7  Register-Exchange Window  Similar to Trellis diagram.  Register set 0 to 3 is multiplexed twice to share K=4 and K=6.  Window length is 36.  Final output are majority voted.

8. Topics on Communication Modem Design VLSI Design Automation LAB8  Controller  Store parameters and provide to inner module.  To control output enable, use counter.  Output enable is 1 when counter value is over 37, and below 37+packet length.

9. Topics on Communication Modem Design VLSI Design Automation LAB9  Running Example ( Xilinx xc4vlx100-12ff1513)  4 packets : length is 1000, 1000, 2000, 4000, and K is 4, 6, 6, 4.  Clock speed is 144.8MHz, 289.6Mbps for input.  Each packet output has 39 clock delay. 1 clock for BM calculation, 2 clock for ACS calculation, 36 clock for RE window.

10. Topics on Communication Modem Design VLSI Design Automation LAB10  Performance and Results  Xilinx xcv2000e-8bg560 : 29896gates, 97.7MHz, 195.4Mbps  Xilinx xc4vlx100-12ff1513 : 26902gates, 144.8MHz, 289.6Mbps  Synthesized in ISE8.2, and post Place & Route simulated in Modelsim.  BER is below 10 -5 when SNR is 6dB for K=6, 6.5dB for K=4.

11. Topics on Communication Modem Design VLSI Design Automation LAB11  Reference  T.K.Truong, Ming-Tang Shih, Irving S.Reed, E.H. Satorius, "A VLSI Design for a Trace-Back Viterbi Decoder", IEEE Trans. on Communications, vol. 40, pp.616-624, March 1992.  Dalia A.El-Dib, Mohamed I.Elmasry, “Low-Power Register-Exchange Viterbi Decoder for High-Speed Wireless Communications", IEEE International Symposium on Circuits and Systems, vol. 5, May 2002.  Dalia A. El-Dib, Mohamed I. Elmasry, “Modified Register-Exchange Viterbi Decoder for Low-Power Wireless Communications”, IEEE Trans. on Circuits and Systems VOL. 51, NO. 2, Feb. 2004  Jun Tang, Keshab K.Parhi, “Viterbi Decoder for High-Speed Ultra-Wideband Communication Systems”, IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 5, 2005.  Andries P. Hekstra, “An Alternative to Metric Rescaling in Viterbi Decoders”, IEEE Trans. on Communications, vol. 37, no. 11, Nov. 1989.  Ranjan Bose, “Information Theory, Coding and Cryptography”, McGrawHill, 2003  DS-UWB Physical Layer Submission to 802.15 Task Group 3a, IEEE P802.15- 04/0137r5