1. Presented by Reconfigurable HPC Research at ORNL using Field-Programmable Gate Arrays (FPGAs) Olaf O. Storaasli Future Technologies Group Computer Science and Mathematics

2. 2 Storaasli_ReconfigHPC_0611 Contents  Background: Why FPGAs?  ORNL experience: FPGA systems/compilers and applications  ORNL partners: Research Lab,, SRC,, THE SUPERCOMPUTER COMPANY Explore FPGAs for future ORNL HPC Virtex4 FPGA blades to “accelerate mission-critical applications > 100x” Steve Scott, CTO HPCWire 24/3/0606 “After exhaustive analysis, Cray concluded that, although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multithreading and hardware accelerators (e.g., FPGAs or ClearSpeed co-processors) creates the greatest opportunity for application acceleration.” ORNL potential benefit: Exceed petaflop goal (reduce power) High-performance computing vendors adopting FPGAs

3. 3 Storaasli_ReconfigHPC_0611 FPGA Logic slice What’s an FPGA? “User-tailored chip” Xilinx Virtex4 FPGA: 25K slices (miniCPUs)  Logic array: user-tailored to application  On-chip RAM, multipliers, and PowerPC CPUs  Mega-gigabit transceivers and digital signaling processing blocks  Supports 100–1000 operations/clock cycle

4. 4 Storaasli_ReconfigHPC_0611 FPGA Virtex4 Pentium Why FPGAs?  Performance—optimal silicon use (maximize parallel ops/cycle)  Rapid growth—gates, speed, I/O  Low power—1/10th CPUs  Flexible—tailor to application 1000 800 600 400 200 0

5. 5 Storaasli_ReconfigHPC_0611 Cray XD1Bee2 (via Xilinx) ORNL FPGA hardware/compilers  SRC-6 (Carte), Digilent (Viva, VHDL), Nallatech (Viva)  Cray XD1 (MitrionC, DSPlogic/Matlab): 6 FPGAs + 144 Opterons  SGI RASC-Altix/Virtex4s (MitrionC)  Bee2: 5 FPGAs and CHiMPS (via Xilinx), DRC (future)

6. 6 Storaasli_ReconfigHPC_0611 Find parallelism: 80% FFTs More GF/$ GF/Watt Goal Profile Model faster Porting HPC code spectral transform shallow water model to FPGAs FTRNDE FTRNPE FTTdd UV FFT SHTRNS FFT COMP1 STEP FTRNEX FTRNVX 8 calls in parallel 3 functions in parallel 2 calls in parallel HLL compiler CHiMPS, Mitrion (FPGA Tools Inside) FPGA speedup HLL developer profiles

7. 7 Storaasli_ReconfigHPC_0611 Viva: Graphical Icons—3-dimensionalMitrionC: Text/flow—1-dimensional Exploring programming options Gauss matrix solver Compiler, simulator, and debugger + Carte/SRC, CHiMPS-VHDL/Xilinx,

8. 8 Storaasli_ReconfigHPC_0611 Simulate molecular dynamics: Compute Ewald particle mesh (FORTRAN) Speedup over Intel 2.8 GHz Xeon host 23,558 atoms61,641 atoms 1st Version + memory tailored 1st Version + memory tailored Compute only 3.30 3.97 Setup + compute 3.29 3.96 Compute + data transfer 0.643.200.693.83 Overall 0.603.190.603.82 Speedup increase with problem size Amber speedup on SRC-6

9. 9 Storaasli_ReconfigHPC_0611 Speedup projections

10. 10 Storaasli_ReconfigHPC_0611 Summary  ORNL FPGA research: - Increasingly relevent to HPC - FPGA Systems: Cray, SRC, Nallatech, Digilent, SGI, Bee2 - Compilers: Mitrion-C, Carte, Viva, CHiMPS, DSPlogic - Application speedup: Amber, STSWM, BLAST, SW,… - Partners: Xilinx HPC team, UT, Mitrion, Cray  Next: Evaluate application performance, test DRC Acknowledgement: This research is supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC05-00OR22725

11. 11 Storaasli_ReconfigHPC_0611 Contact Olaf Storaasli Future Technologies Group Olaf@ornl.gov 11 Storaasli_ReconfigHPC_0611