1. Latest from the SiLC R&D Aurore Savoy-Navarro, LPNHE-Paris/IN2P3-CNRS On behalf of the SiLC collaboration: U. of Michigan, UCSC-Santa Cruz, IMB-CNM/CSIC, U. of Geneva, U. of Helsinki, IEKP Karlsruhe, Moscow State U., Obninsk State U., LPNHE-Paris, Charles U.- Prague, IFCA-Santander, IFIC-Valencia/CSIC, HEPHY-Vienna, Kyungpook U., Yonsei U., Korean U., Seoul Nat. U., SungKyunKwan U., Tokyo U., Torino U., Hamamatsu, and close connections with: EUDET EU program, FNAL and SLAC (DOE contracts); collaborative contacts with CERN (in progress) SiLC Satellite meeting on: Nov. 18 from 9h am to 5h pm in Franz-Josef room II http://wwwhephy.oeaw.ac.at/p3w/ilc/ws05/wframe.html

2. R&D Goals Very high precision on momentum and spatial measurements Low material budget Robustness Easy to build and to work with Low cost SiLC is a generic R&D collaboration to develop the next generation of large area Silicon Detectors for the ILC; It applies to all the detector concepts and indeed gathers teams from all 3 detector concepts:  SILC R&D offers a unique framework to compare tracking performances between the various detector concepts.  Main difference between the detector concepts = tracking system SiD GLD LDC

3. To achieve these goals:  R&D on sensors  R&D on Electronics  R&D on Mechanics together with developing the appropiate tools:  Test benches  Calibrations and Monitoring  Simulations  Test Beam

4. Silicon Envelope surrounding TPC SiD: all Si-tracker TPC volume 4 4 Si tracking components in detector concept with TPC internal and external Si tracking components in barrel and large angle (forward/end caps) regions, acting as intermediate trackers and forming a complete coverage Si tracking system How it compares with SiD tracker? Si tracking components in a detector with central TPC

5. R&D on Sensors  Silicon strips are the baseline with: Larger size wafers, single and double sided Thinner/Thinning Smaller pitch High yield Eventually different shapes Possibility to use new technos in some regions:  Possibility to use new technos in some regions: Pixelization: Pixels, DEPFET, MAPS/FAPS, SOI In order to achieve this R&D:  Lab test bench for full characterization of the sensors (most Labs in SiLC) with a continuous upgrade.  Fabrication line for new ideas on sensors at various Institutes (Korean Institutes, Helsinki U., IMB-CNM/CSIC)  Process Quality Control and sensor characterization (Vienna, Karlsruhe, Korea, Helsinki)  Medium size fab line for small size production (looking at different such places, in Europe and Asia for the time being)  Transfer to Industry for full production (presently Hamamatsu but could evolve).

6. Tests & results on Si strips VA64_hdr Tsh=3.7µs 28cm x N=1,4 S/N=20/30, Lstrip=28cm Collaboration Paris-Prague Ladder strips variable L, built by Geneva U. Laser and radioactive source tests at Paris test bench S/N=12/18, Lstrip=56cm S/N measured for L strip : 28, 56, 112, 224 cm Results by SiLC meeting Next step: S/N with new FE chip vs VA1 chip on new ladder prototype (see next) Then go to test beam.

7. Development of fabrication line for new sensors Development of fabrication line for new sensors Several Institutions in SILC(incl. Helsinki U.) are developing new sensor research lines Strategy:  The research Labs develop & test new ideas  transfer to small fabs for reduced prod.  Large production, high quality and reliability: HAMAMATSU Monopoly Ex1: 5’’ DSSD fab. line in Korean U. (see Hitoshi’s presentation @SiLC meeting) Ex2: rad hard sensor techno at IMB-CNM

8. R&D on Electronics The Si tracking system includes: a few 100m 2, a few 10 6 strips Events tagged every bunch (300ns) during the overall train (1 ms) Data taking/pre-processing ~ 200 ms Occupancy: < a few % Requested features for FE chip: Low noise preamplifiers Shaping time (from 0.5 to 5 µs, depending the strip length) Analogue sampling Highly shared ADC Digitization @ sparsification Very low power dissipation Power cycling Compact and transparent Choice of DSμE & go to VDSM First LPNHE prototype fulfills most of these requirements Other electronics issues: Time measurement Calibration/Monitoring of the electronic chain Connectics Cabling Integration into DAQ Data taking/pre-processing On detector Outside detector Bunch tagging Will be discussed at the SiLC Meeting, Friday Nov. 18th

9. Two FE designs (SiLC) SCIPP-UCSC (0.25µ TSMC techno) Double-comparator discrimination system  Charge by TOT  Improve spatial resolution (25%) Functionality proof presented@Snowmass LPNHE-Paris: Analogue sampling+A/D, including sparsification on sums of 3 adjacent strips. 180 nm UMC DSM techno. First chip successfully submitted tests mostly achieved Next version: in progress Also a FE chip underway for SiD: see B. Cooper’s talk & JF Genat at SiLC meeting

10. LPNHE chip: layout results & tests 3 mm 1.6 mm 10 chips tested with continuous feedback between simulations & measurements-> results well understood Only failure: On chip #8, comparator does not work. Preamplifier Gain: 8mV/MIP as expected: OK Dynamic range: 50 MIP as expected: OK Linearity: +/-1.5% expected: +/-0.5 70 µW power dissipation Noise: 498 + 16.5 e-/pF 490 + 16.5 e-/pF expected: OK Shaper: Waveform: 2-6 ms expected 1-10 ms Noise: 650 + 10.5 e-/pF meas. 350 e- + 10 e-/pF exptd 110 µW power dissipation the layout: 16 +1 ch.(Nov 04)The chip (Feb 05)the test board Process spread: 3.3% (multiproject) Thus quite good: UMC 180nm CMOS is proven to be robust proven to be robust CMS technology CMS technology TESTS & RESULTS

11. 128 channel chip UMC 130 nm CMOS techno with sampling included; 2nd chip prototype under design, submission Sept 06 (preproto 4-8 channel-chip, submitted March 06). Will equip the test beam prototypes Second LPNHE FE chip prototype: underway (See JF Genat’s talk at SiLC meeting) analogue

12. R&D on Mechanics concentrates on:  CAD design of Si tracking components: essential for baseline design studies of detector concepts  Elementary module design in close collaboration with FE electronics designers  Large structure: robust, light, easy to build  Materials  Positioning & alignment  Cooling  Robotisation & Industry transfer  Integration issues For all these items new solutions must be found

13. Barrel Internal barrel + forward TPC µvertex zone SIT zone FTD zone Thermal insulation 30 cm Microvertex zone includes: µvertex + 2 disks with same pixel technology SIT zone includes: 2 or 3 Si layers + 2 disks strips and /or pixel techno FTD zone includes: at least 3 more disks extending from 60cm to 150cm or up to the end of TPC length with eventually more disks The ensemble {µvertex + SIT +FTD} is inside a thermal insulation (under study) Nb of layers and disks & preferred techno are being studied (preliminary simulations studies: M. Berggren) Tiles vs Ladders ? SET if TPC ? How? CAD & main issues for Si components: detector design & performances

14. Ø203 mm ~405m m 270m m 230m m 59mm 104m m ~117m m ~157m m sens or Projective XUV …….. FE electronics foam Si + support EndCapTk Ladders with 3 or 2 sensors Outer ECT layers: Projective vs XUV ? Nb of layers? How to arrange them? (simu studies) How many layers? If TPC: layers set up? TPC+ Si &/or Calo + Si Level arm?(simu studies) ~1 – 1.3 m Mechanical team LPNHE-Paris

15. Elementary modules: to be totally revisited! Ladder with 1 to 3 sensors 0.7%X0 Next step = chip inserted onto the detector: connectics/VDSM/cabling issues (study starting: see SiLC meeting) Modules: light, precise, robust, easy to build & assemble New sensors (next generation) Support: materials & design FE electronics connectics, packaging and cabling Module positioning on large size support structure Easy to build (robotisation ?) Industry Transfer (large #) Universal sensor vs diff. types Be innovative! N.B. This is just a very first ladder prototype: just a very preliminary exercise… By no means what will be the final one!! Old fashioned FE electronics!!

16. AMS handmade ladder production line Automatized Automatized production line at CMS Starting point: both expertise exist within SiLC; Need to be further developped Robotic assembly Probe station LADDER PRODUCTION LINE: examples Geneva University & ETH Zurich

17. LIGHT COOLING (?): Thermo mechanical studies External Temp: 45°C Si detector temp: 30°C Cooling water Temp: 20°C Cu screen: ~25°C 1h2h8h Temp. probes Foam insulator & cooling screen (high module C fiber) with water cooling is OK (LPNHE-Paris)

18. The tools:  Lab test benches: Dedicated test bench to be developed to test: VDSM chips, cooling studies, position monitoring and alignements, sensor characterization etc… Facilities already existing in some case have to be further developed/adapted to new developed techniques.  Test beams  Test beams (see next & Z. Dolezal’s talk at SiLC meeting)  Simulations  Simulations (see next & M. Berggren’s talk)  Position Monitoring and Alignment (Michigan U., IFCA-Santander) Presently two complementary systems: C. Rivero’s presentation at SiLC Meeting on Friday.

19. SIMULATIONS G4 geometry of the Si Envelope (V. Saveliev, Obninsk St U.) Ext. FWD Ext. FWD Ext Barrel Int. Barrel+FWD DB description in G4 thanks to the detailed CAD Occupancies calculated with BRAHMS full simulation (Si-Envelope+TPC), Higgstrahlung HZ with bbbar and q qbar at Ecm=500 GeV Values at most of order a few% for the hotest places in the detector! Thus medium size ladder looks to be appropriate.

20. Higgs event in the SiD detector design, using MOKKA G4 framework SiD detector included in geometry DB (V. Saveliev) A lot of work performed with fast but enough detailed simulation (SGV): See talk by M. Berggren But dramatically lacking a full reconstruction program in the G4 framework for complete detector concept studies

21. Test beam: Detector Prototypes Support mobile Design (just started) Fabrication Assembling & Mounting Module with 3 sensors Module with 2 sensors Second layer partly covering the first one. Total of 60 trapezoidal sensors, About 10 K readout channels Ready by end 2006/beg. 2007 Other prototypes: Ladders of different sizes and sensors Forward Prototype: under CAD study

22. Test beam schedule (SiLC-EUDET) 2007 2006 Preparation: Construction barrel prototype New foundry (>=512 ch + techno) Preparation: Endcap Prototype with 128 channels (130 nm CMOS-UMC) 200820092005 DESY CERN? CERN or FNAL? Preparation Ladders+ FE tests 2 ladders, 1st proto chips Tests End Cap proto(s), with 2nd foundry chips Tests barrel proto also combined with other sub detectors and new foundry These coming 4 years: 2006 to 2009 will be essential to the development of this R&D: the test beams will be instrumental to test new ideas and new prototypes on all the different aspects of this R&D (sensors, electronics, & mechanics). Look for combined test with other subdetectors. Synergy with LHC now and for future upgrade.

23. SiLC Satellite Meeting Thomas Bergauer, Manfred Krammer and Aurore Savoy-Navarro Friday November 18, 2005 from 9h am to 5h pm in the ILC-ECFA Workshop place, Franz-Josef room II http://wwwhephy.oeaw.ac.at/p3w/ilc/ws05/wframe.html Visit to the sensor test center and module production for the CMS tracker will be arranged during the workshop For much more on the ongoing work and future developments