1. PXD DAQ in Giessen 1. How we do programming 2. Proposal for link layer Bonn+Giessen Meeting, Feb 2, 2011

2. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 2 The Belle-II people in the group  Thomas Geßler, Doktorand  David Münchow, Doktorand  Björn Spruck, Postdoktorand  Sören Lange, beta tester, paper work  Wolfgang Kühn  Ming Liu, Lu Li, Ph. D. students from Stockholm, on sabattical here -> advisors for debugging  Lots of help from Qiang Wang, Zhen-An Liu (IHEP)

3. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 3 Approach: put programming platform into virtual machines in 2 virtual machines (VirtualBox) virtual machine #1: WinXP XPS (XILINX platform studio), EDK, IMPACT all download drivers (USB is forwarded to host machine!) all licenses virtual machine #2: Ubuntu ELDK (embedded Linux) with PowerPC cross compiler and PowerPC Linux filesystem (NFS mountable) 3 platforms supported ML403 board, Virtex-4 FX12 ML405 board, Virtex-4 FX20, (optical link) ATCA Compute Node, Virtex-4 FX-60 (many peripherals)

4. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 4 3 platforms supported

5. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 5 The basic programming sequence  XILINX Platform Studio (XPS) peripherals, connections (PLB), VHDL code etc.  „device tree generator“ as additional script generates e.g. „ml405.dts“  generates the bitstream („download.bit“)  ELDK  cross-compiles the Linux kernel generates „kernel.elf“  needs the device tree file as input (e.g. is the PowerPC connected to Ethernet, RAM, etc.?)  IMPACT upload „download.bit“ to JTAG  XMD (XILINX memory debugger, in a MS-DOS window) > dow kernel.elf Virtual machine #1 (WinXP) #2 (Ubuntu) #1 (WinXP) #1 (WinXP) Pre-step: standard cores (e.g. RocketIO, aurora) by „ISE Core Generator“.

6. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 6 device tree files Example: virtual machine #2, ELDK PowerPC cross compiler

7. Optical Links

8. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 8 Optical Links on CNs  8 optical links on each CN  Xilinx RocketIO-based (-10 chip up to 3.125 Gbps, -11&-12 up to 6.25 Gbps)  @2 Gbps (8b/10b)  Finisar FTLF8519P2BNL  Up to 2.125 Gbps bi-directional  Hot-pluggable SFP footprint  ~ 70$ each Slide by Ming Liu

9. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 9 Optical IP Core Design  Standard PLB IP core  Master transfer support  Intr. Coalescing Support  Run at full speed (2 Gbps = 200 MB/s) Slide by Ming Liu

10. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 10 System Architecture (HADES) Slide by Ming Liu

11. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 11 Optical Test  First P2P test of CNs for the HADES DAQ and trigger system  @2 Gbps with Trigger & Readout Board 2 (TRB2)  Pseudo-random data  150 hours, 0 bit error Test and firmware by Qiang Wang and Ming Liu

12. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 12 Status of optical link  Generating rocketio core qith aurora 8B/10B modelsim project, chipscope project, bitstream upload to ML405 = o.k.  Not solved yet:  start transmission procedure (synchronizing etc.)  polarity issues  how to configure the „elastic buffer“?  Qiang says, „be careful, TRB code uses external chips“

13. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 13  QLOGIC ISP2312 singlePort 2GB PCI-X Fibre Channel-HP-Se  FibreChannel Karte aus einem HP DL580 G3 Server.  Bezeichnungen auf der Karte:  FTRJ-8519F1-2.5 850nm  S/N: H12AYA4 03-25  Class 1 Laser 21 CFR(J)  Finisar  P59270BRAP2G5X

14. Proposal for optical link layer protocol (working approach)

15. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 15 Temporary Proposal for Bonn-Gießen link layer based on the optical test with HADES TRB Board  Aurora 2 byte + align 2 byte (for 16 bit)  MGT110A [GT11_XTY3]  REFCLK1 (not low speed REFCLK2) 200 MHz  8B/10B  clock correction YES  PLL use calibration block YES, DCLK 50 MHz (= max.)  Use internal AC coupling for receiver YES  To be defined:  K characters ?  00000 000 idle code ?

16. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 16

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21. Belle-II TDAQ Beijing Jan 2011Giessen Team | Status of ATCA based System 21

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