1. 處理器設計與實作 CPU LAB for Computer Organization 1

2. LAB 7: MIPS Set-Associative D- cache

3. 實驗目的 1. 認識 data-cache 的功能與運作原理 2. 了解 cache 之 write policies 3. 了解 Set-Associative Cache 結構 4. 實作簡易 Set-Associative Cache 修改操作

4. CPU has the demand for writing and reading data memory, while it has no requirement for writing instruction memory. (Modifying instruction memory is prohibited) As a result, d-cache will be writed and read by CPU and i-cache will be only read. D-cache vs. I-cache

5. Read hits – this is what we want! Read misses – stall the CPU, fetch block from memory, deliver to cache, restart Write hits: – can replace data in cache and memory (write-through) – write the data only into the cache (write-back the cache later) Write misses: – read the entire block into the cache, then write the word (write allocate) – or just write around the cache Hits vs. Misses

6. Write hit – Write-through (WT) – Write-back (WB) Write miss –Write-allocate (or write allocation) –Write-around Write Policy

7. Write-hit policies – Write-through (also called store-through) Write to main memory whenever a write is performed to the cache. – Write-back (also called store-in or copy-back) Write to main memory when the modified data in cache is evicted. Write Policy

8. Write-ThroughWrite-Back Policy Data written to cache block also written to lower- level memory Write data only to the cache Copyback when replacing a dirty copy DebugEasyHard Do read misses produce writes? NoYes Do repeated writes make it to lower level? YesNo

9. Write-miss policies – Write-allocate (or write allocation) Read the missing block from lower level memory into cache, then work as write hit(WT or WB). –Write-around Write the data into next level memory. Write Policy

10. N direct mapped caches in parallel An index gets N blocks N-way set associative

11. Direct Mapped Cache

12. Set-Associative Cache

13. Associativity Associativity is a trade-off. Cache operations with more associativity takes more power, chip area, and potentially time. However, caches with more associativity suffer fewer misses, so that the CPU wastes less time reading from main memory.

14. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss Index 0 1 2 3

15. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss 00Miss Mem[00] Index 0 1 2 3

16. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss 00Miss 20Miss Mem[00] Index 0 1 2 3 Mem[20]

17. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss 00Miss 20Miss 00Hit Mem[00] Index 0 1 2 3 Mem[20]

18. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss 00Miss 20Miss 00Hit 1cMiss Mem[00] Mem[1c] Index 0 1 2 3 Mem[20]

19. 2-Way Associative Example Main MemoryCache The sequence of memory access: 00, 20, 00, 1c, 00 Mem BlockHit/Miss 00Miss 20Miss 00Hit 1cMiss 00Hit Mem[00] Mem[1c] Index 0 1 2 3 Mem[20] Hit Rate = 40%

20. Set-Associative Cache

21. 1.Compusory misses: The block must be brought into the cache on the first access to a block;also called cold start misses. 2.Capacity misses: Blocks are being discarded from cache because cache can’t contain all blocks Needed for program execution. 3.Conflict misses: Conflict misses occur when mutiple blocks are mapped to the same set, and it could not happen in case of fully set associative cache. Types of cache misses

22. Cache optimization Types of cache misses Design changeEffect on miss ratePossible negative performance effect increase cache sizereduce capacity missespossibly increase access time increase associativityreduce conflict missespossibly increase access time increase block sizereduce compulsory misses increase miss penalty

23. When a line must be evicted from a cache to make room for incoming data, the replacement policy determines which line is evicted. The general goal of the replacement policy is to minimize future cache misses by evicting a line that will not be referenced often in the future. Replacement policy

24. Least recently used (LRU) Random Replacement policy

25. Least recently used (LRU) The cache ranks each of the lines in a set according to how recently they have been accessed. Evicts the least-recently used line from a set when an eviction is necessary. Replacement policy

26. Random A randomly selected line from the appropriate set is evicted to make room for incoming data. Studies have shown that LRU replacement generally gives slightly higher hit rates than random replacement, but that the differences are very small for caches of reasonable size. Replacement policy

27. In most systems, caches are meant to be transparent. CPU must stalls while cache fetchs blocks from memory,and CPU leaves the stall state when cache finished fetching. Cache in CPU system

28. 實作 ( 一 ). Direct-mapped Cache

29. 實作 ( 一 )  請同學完成 Direct-mapped cache module (dcache_system.v) 中未完成之接線， 並用 ModelSim 模擬 data cache 行為是否正確，結果會在 下方 transcrpit 視窗中顯示 。  此 cache size 為 16KB ， line size 為 16 Byte  此 cache 之 Write policy 為 Write through 與 Write allocate

30.  依需求把 Addr 訊號線拆成 index, line, tag_in  Addr_mem 為傳給 memory 的 address 請同學完成 tag 之後的其他欄位 實作 ( 一 )

31.  跑模擬看波型來除錯  按下左邊小圖案或工具列 Simulate -> Start Simulation

32. 實作 ( 一 )  打開 work 資料夾，找到 testbench( 如左圖 )  記得把下面的 Enable optimization 打勾取消

33.  對 dcache1 按右鍵，選擇 Add to -> Wave -> All item in region 加入波型  若想要看其他波型，也是對其他 module 做一樣步驟 實作 ( 一 )

34.  Parameter 之使用方法  Verilog 中，宣告一 module 時在前面加上 #( 數字 ) 便能依不同 module 需要 指定不同的數字來產生 module 。  下面兩圖為一使用範例，左圖中的 memc 加上 #(32) 便會在產生 module 時 ( 右圖 ) ，以 Size = 32 取代 Size = 1 ，如此便能靈活改變 port 的大小。 說明 :Parameter in Verilog

35. 實作 ( 二 ). 2-way Set Associative Cache

36. 實作 ( 二 )  修改實作一完成之 Direct-mapped cache ，改為 2-way set associative cache  Cache size 一樣為 16KB ， line size 為 16 Byte (index 需為多少以符合規格 ?)

37. 實作 ( 二 )  2 way set associative 之 DataOut ， tag_out 都變為 2 個，請同學完成 ???? 的部分 以決定 CPU 看到的 DataOut 與 tag_out  numout 為決定寫入哪個 block 之訊號。 block 1 滿了就寫入 block 2 ，若都有資料則 輪流寫入新資料取代舊資料

38. 實作 ( 二 )  模擬驗證的方式同實作一，但除錯時建議新增 2 個 dcache module 訊號以方便 除錯  輸出結果對錯一樣會顯示在 ModelSim 下方的 transcript 中  請同學們比較 hit rate 與實作一有何不同

39. 挑戰題. Write Back Cache

40. 挑戰題  請同學修改 writeback 資料夾的 control unit(dcache_ctrl.v) ，使 cache 之 Write policy 從 Write through 改為 Write back (write miss policy 都為 write around)  各 state 與各控制訊號意義能在 dcache_ctrl.v 裡的註解裡看到，請同學依後面 所提供的 Write-back cache state, 在 output logic 區塊中正確的位置加上 (cs==WB), 調整 write back state 狀態該有的控制訊號輸出  模擬後 transcript 會顯示結果正不正確, 波行圖中 cs 訊號線要出現 c 與 a(16 進位 ) 才代表有出現 write back

41. 挑戰題 – Write through 狀態圖

42. 挑戰題 – Write back 狀態圖