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Point of Load (PoL) GaN: criteri di progetto e test in laboratorio Giorgio Spiazzi University of Padova Dept. of Information Engineering – DEI.

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Presentation on theme: "Point of Load (PoL) GaN: criteri di progetto e test in laboratorio Giorgio Spiazzi University of Padova Dept. of Information Engineering – DEI."— Presentation transcript:

1 Point of Load (PoL) GaN: criteri di progetto e test in laboratorio Giorgio Spiazzi University of Padova Dept. of Information Engineering – DEI

2 Objectives Realization of a PoL converter employing GaN power MOSFETs (EPC2015, 40V, 33A, 4m  ) Specifications: Minimum input voltage:V gmin = 8 V Maximum input voltage:V gmax = 19 V Output voltage (0.6V  5.5V):V o = 1.2 V Output current:I o = 10 A* Switching frequency:f sw = 1 MHz *Limited by thermal considerations

3 PoL GaN Synchronous Buck converter Dedicated half-bridge gate driver (LM5113) Lossless inductor DCR current sensing DC/DC controller LTC3833 Near 0% and 100% duty-cycle values

4 Inductor DCR current sensing Pros: Exploits the inherent inductor parasitic resistance No need for external sensing resistor Cons: Needs differential voltage sensing Temperature sensitive sensing resistor

5 Inductor DCR current sensing Inductor current: Capacitor voltage:

6 Inductor DCR current sensing Inductor current:Capacitor voltage: Goal: match time constants Max differential signal:

7 Inductor DCR current sensing Scale factor If V m_max exceeds differential amplifier input range:

8 LTC 3833 controller

9 Differential output voltage sensing (allows output ground deviations of  500mV respect to local ground)

10 LTC 3833 controller INTV CC / EXTV CC Power (if EXTV CC < 4.6V an internal 5.3V LDO supplies INTV CC power from V IN )

11 LTC 3833 controller 0.75V < V RUN < 1.2V = standby mode (only driver disabled, I Q = 2mA) V RUN < 0.75V = shutdown (I Q = 15  A)

12 LTC 3833 controller V TRACK/SS < 0.6V = startup (It can be driven by another power supply in a master-slave configuration)

13 LTC 3833 controller Controlled On-Time Valley Current Mode architecture (Top switch turned on for a fixed time interval, adjusted by a PLL, when the inductor current reaches a threshold during bottom switch conduction interval) Threshold provided by output voltage error amplifier

14 LTC 3833 controller MODE/PLLIN = 0 discontinuous mode operation (Comparator I REV detects a negative inductor current and turn off bottom switch. If a constant voltage or a clock signal is applied to MODE/PLLIN, CCM operation is maintained)

15 LTC 3833 controller Switching frequency set by R T (from 200kHz to 2MHz)

16 LTC 3833 controller PGOOD when 0.925 V oNOM < V o < 1.075 V oNOM (Overvoltage protection not shown)

17 LTC 3833 controller V RNG sets maximum voltage V SENSE+ -V SENSE- (30mV when tied to SGND, 50mV when tied to INTV CC, any value between 30mV and 100mV using a resistor divider)

18 Power stage & control scheme INTV CC supplies the driver Dead time adjust

19 Inductor design Peak-to-peak current ripple: Assuming V IN = 12V and  i L = 5A: Selected value: L = 220 nH

20 TOP layer GND +V o +V IN GaN J1J1 J3J3 J4J4 J2J2 J5J5 J6J6 Driver (bottom)

21 TOP layer EPC2015 Inductor (220nH) GND +V o +V IN GaN Ext V dd V dd select J1J1 Dead time adjust Output cap v GS v sw J3J3 J3J3

22 BOTTOM layer GND +V o +V IN Driver GND Controller GaN (top)

23 BOTTOM layer GND +V o +V IN Driver GND Controller LTC3833 Controller LM5113 Driver Input cap Output cap

24 Experimental measurements Prototype N°1: V in = 12V, I o = 10A

25 Experimental measurements Prototype N°1: V in = 12V, I o = 10A (Zoom) Dead times

26 Efficiency Output current [A]

27 Thermal image Prototype N°1: V in = 12V, I o = 10A 74°C (top switch) 90°C (bottom switch) 64°C (inductor)

28 Conclusions A 1.2V-10A PoL converter employing EPC2015 GaN power MOSFETs have been designed. Two 2-layer PCB prototypes have been built and tested. Maximum output current is limited by thermal performance. Test at LASA…………….(to be done)


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