1. Samira Khan University of Virginia Feb 2, 2016 COMPUTER ARCHITECTURE CS 6354 Fundamental Concepts: ISA Tradeoffs The content and concept of this course are adapted from CMU ECE 740

2. AGENDA Literature survey for projects Review from last lecture Fundamental concepts – ISA Tradeoffs 2

3. RESEARCH PROJECT Your chance to explore in depth a computer architecture topic that interests you Perhaps even publish your innovation in a top computer architecture conference. Start thinking about your project topic from now! Interact with me and the TA Read the project topics handout well Groups of 2-3 students (will finalize this later) Proposal due: Feb 18 3

4. LITERATURE SURVEY Goal: Critically analyze related work to your project Pick three papers related to your project Use the same format as the reviews – What is the problem the paper is solving – What is the key insight – What are the advantages and disadvantages – How can you do better Send the list of the papers to the TA by Feb 7 Reviews due on Feb 13, 2016 Will help you to formulate the project 4

5. THE IMPORTANCE OF WORKING ON IMPORTANT PROBLEMS 5 You and Your Research

6. LAST LECTURE RECAP SIMD – Array – Vector Systolic Architecture ISA Trade offs 6

7. REVIEW: VECTOR PROCESSORS Advantages + No dependencies within a vector – Pipelining, parallelization work well – Can have very deep pipelines, no dependencies! + Each instruction generates a lot of work – Reduces instruction fetch bandwidth + Highly regular memory access pattern – Interleaving multiple banks for higher memory bandwidth – Prefetching + No need to explicitly code loops – Fewer branches in the instruction sequence Disadvantages -Works (only) if parallelism is regular (data/SIMD parallelism) -What happens when we search a linked list? -Memory (bandwidth) can easily become a bottleneck, especially if - data not mapped properly 7

8. H. T. Kung, “Why Systolic Architectures?,” IEEE Computer 1982. Memory: heart PEs: cells Memory pulses data through cells REVIEW: SYSTOLIC ARRAYS 8

9. Advantage: – Specialized (computation needs to fit PE organization/functions)  improved efficiency, simple design, high concurrency/ performance  good to do more with less memory bandwidth requirement Downside: – Specialized  not generally applicable because computation needs to fit the PE functions/organization 9

10. ISA VS. MICROARCHITECTURE What is part of ISA vs. Uarch? – Gas pedal: interface for “acceleration” – Internals of the engine: implements “acceleration” – Add instruction vs. Adder implementation Implementation (uarch) can be various as long as it satisfies the specification (ISA) – Bit serial, ripple carry, carry lookahead adders – x86 ISA has many implementations: 286, 386, 486, Pentium, Pentium Pro, … Uarch usually changes faster than ISA – Few ISAs (x86, SPARC, MIPS, Alpha) but many uarchs – Why? 10

11. ISA Instructions – Opcodes, Addressing Modes, Data Types – Instruction Types and Formats – Registers, Condition Codes Memory – Address space, Addressability, Alignment – Virtual memory management Call, Interrupt/Exception Handling Access Control, Priority/Privilege I/O Task Management Power and Thermal Management Multi-threading support, Multiprocessor support 11

12. Microarchitecture Implementation of the ISA under specific design constraints and goals Anything done in hardware without exposure to software – Pipelining – In-order versus out-of-order instruction execution – Memory access scheduling policy – Speculative execution – Superscalar processing (multiple instruction issue?) – Clock gating – Caching? Levels, size, associativity, replacement policy – Prefetching? – Voltage/frequency scaling? – Error correction? 12

13. ISA-LEVEL TRADEOFFS: SEMANTIC GAP Where to place the ISA? Semantic gap – Closer to high-level language (HLL) or closer to hardware control signals?  Complex vs. simple instructions – RISC vs. CISC vs. HLL machines FFT, QUICKSORT, POLY, FP instructions? VAX INDEX instruction (array access with bounds checking) – Tradeoffs: Simple compiler, complex hardware vs. complex compiler, simple hardware – Caveat: Translation (indirection) can change the tradeoff! Burden of backward compatibility Performance? – Optimization opportunity: Example of VAX INDEX instruction: who (compiler vs. hardware) puts more effort into optimization? – Instruction size, code size 13

14. X86: SMALL SEMANTIC GAP: STRING OPERATIONS REP MOVS DEST SRC How many instructions does this take in Alpha? 14

15. SMALL SEMANTIC GAP EXAMPLES IN VAX FIND FIRST – Find the first set bit in a bit field – Helps OS resource allocation operations SAVE CONTEXT, LOAD CONTEXT – Special context switching instructions INSQUEUE, REMQUEUE – Operations on doubly linked list INDEX – Array access with bounds checking STRING Operations – Compare strings, find substrings, … Cyclic Redundancy Check Instruction EDITPC – Implements editing functions to display fixed format output Digital Equipment Corp., “VAX11 780 Architecture Handbook,” 1977-78. 15

16. SMALL VERSUS LARGE SEMANTIC GAP CISC vs. RISC – Complex instruction set computer  complex instructions Initially motivated by “not good enough” code generation – Reduced instruction set computer  simple instructions John Cocke, mid 1970s, IBM 801 – Goal: enable better compiler control and optimization RISC motivated by – Memory stalls (no work done in a complex instruction when there is a memory stall?) When is this correct? – Simplifying the hardware  lower cost, higher frequency – Enabling the compiler to optimize the code better Find fine-grained parallelism to reduce stalls 16

17. SMALL VERSUS LARGE SEMANTIC GAP John Cocke’s RISC (large semantic gap) concept: – Compiler generates control signals: open microcode Advantages of Small Semantic Gap (Complex instructions) + Denser encoding  smaller code size  saves off-chip bandwidth, better cache hit rate (better packing of instructions) + Simpler compiler Disadvantages - Larger chunks of work  compiler has less opportunity to optimize - More complex hardware  translation to control signals and optimization needs to be done by hardware Read Colwell et al., “Instruction Sets and Beyond: Computers, Complexity, and Controversy,” IEEE Computer 1985. 17

18. HOW HIGH OR LOW CAN YOU GO? Very large semantic gap – Each instruction specifies the complete set of control signals in the machine – Compiler generates control signals – Open microcode (John Cocke, 1970s) Gave way to optimizing compilers Very small semantic gap – ISA is (almost) the same as high-level language – Java machines, LISP machines, object-oriented machines, capability-based machines 18

19. EFFECT OF TRANSLATION One can translate from one ISA to another ISA to change the semantic gap tradeoffs Examples – Intel’s and AMD’s x86 implementations translate x86 instructions into programmer-invisible microoperations (simple instructions) in hardware – Transmeta’s x86 implementations translated x86 instructions into “secret” VLIW instructions in software (code morphing software) Think about the tradeoffs 19

20. ISA-LEVEL TRADEOFFS: INSTRUCTION LENGTH Fixed length: Length of all instructions the same + Easier to decode single instruction in hardware + Easier to decode multiple instructions concurrently -- Wasted bits in instructions (Why is this bad?) -- Harder-to-extend ISA (how to add new instructions?) Variable length: Length of instructions different (determined by opcode and sub-opcode) + Compact encoding (Why is this good?) Intel 432: Huffman encoding (sort of). 6 to 321 bit instructions. How? -- More logic to decode a single instruction -- Harder to decode multiple instructions concurrently Tradeoffs – Code size (memory space, bandwidth, latency) vs. hardware complexity – ISA extensibility and expressiveness – Performance? Smaller code vs. imperfect decode 20

21. ISA-LEVEL TRADEOFFS: UNIFORM DECODE Uniform decode: Same bits in each instruction correspond to the same meaning – Opcode is always in the same location – Ditto operand specifiers, immediate values, … – Many “RISC” ISAs: Alpha, MIPS, SPARC + Easier decode, simpler hardware + Enables parallelism: generate target address before knowing the instruction is a branch -- Restricts instruction format (fewer instructions?) or wastes space Non-uniform decode – E.g., opcode can be the 1st-7th byte in x86 + More compact and powerful instruction format -- More complex decode logic (e.g., more logic to speculatively generate branch target) 21

22. X86 VS. ALPHA INSTRUCTION FORMATS x86: Alpha: 22

23. ISA-LEVEL TRADEOFFS: NUMBER OF REGISTERS Affects: – Number of bits used for encoding register address – Number of values kept in fast storage (register file) – (uarch) Size, access time, power consumption of register file Large number of registers: + Enables better register allocation (and optimizations) by compiler  fewer saves/restores -- Larger instruction size -- Larger register file size -- (Superscalar processors) More complex dependency check logic 23

24. ISA-LEVEL TRADEOFFS: ADDRESSING MODES Addressing mode specifies how to obtain an operand of an instruction – Register – Immediate – Memory (displacement, register indirect, indexed, absolute, memory indirect, autoincrement, autodecrement, …) More modes: + help better support programming constructs (arrays, pointer- based accesses) -- make it harder for the architect to design -- too many choices for the compiler? Many ways to do the same thing complicates compiler design Read Wulf, “Compilers and Computer Architecture” 24

25. X86 VS. ALPHA INSTRUCTION FORMATS x86: Alpha: 25

26. x86 register absolute register indirect register + displacement 26

27. x86 indexed (base + index) scaled (base + index*4) 27

28. OTHER ISA-LEVEL TRADEOFFS Load/store vs. Memory/Memory Condition codes vs. condition registers vs. compare&test Hardware interlocks vs. software-guaranteed interlocking VLIW vs. single instruction vs. SIMD 0, 1, 2, 3 address machines (stack, accumulator, 2 or 3-operands) Precise vs. imprecise exceptions Virtual memory vs. not Aligned vs. unaligned access Supported data types Software vs. hardware managed page fault handling Granularity of atomicity Cache coherence (hardware vs. software) … 28

29. THESE SLIDES WERE NOT COVERED IN THE CLASS, BUT FOR YOUR BENEFIT 29

30. PROGRAMMER VS. (MICRO)ARCHITECT Many ISA features designed to aid programmers But, complicate the hardware designer’s job Virtual memory – vs. overlay programming – Should the programmer be concerned about the size of code blocks? Unaligned memory access – Compile/programmer needs to align data Transactional memory? VLIW vs. SIMD? Superscalar execution vs. SIMD? 30

31. TRANSACTIONAL MEMORY enqueue (Q, v) { Node_t node = malloc(…); node->val = v; node->next = NULL; acquire(lock); if (Q->tail) Q->tail->next = node; else Q->head = node; Q->tail = node; release(lock); } begin-transaction … enqueue (Q, v); //no locks … end-transaction THREAD 1THREAD 2 enqueue (Q, v) { Node_t node = malloc(…); node->val = v; node->next = NULL; acquire(lock); if (Q->tail) Q->tail->next = node; else Q->head = node; Q->tail = node; release(lock); } enqueue (Q, v) { Node_t node = malloc(…); node->val = v; node->next = NULL; acquire(lock); if (Q->tail) Q->tail->next = node; else Q->head = node; release(lock); Q->tail = node; } enqueue (Q, v) { Node_t node = malloc(…); node->val = v; node->next = NULL; acquire(lock); if (Q->tail) Q->tail->next = node; else Q->head = node; release(lock); Q->tail = node; } begin-transaction … enqueue (Q, v); //no locks … end-transaction 31

32. TRANSACTIONAL MEMORY A transaction is executed atomically: ALL or NONE If there is a data conflict between two transactions, only one of them completes; the other is rolled back – Both write to the same location – One reads from the location another writes 32

33. ISA-LEVEL TRADEOFF: SUPPORTING TM Still under research Pros: – Could make programming with threads easier – Could improve parallel program performance vs. locks. Why? Cons: – What if it does not pan out? – All future microarchitectures might have to support the new instructions (for backward compatibility reasons) – Complexity? How does the architect decide whether or not to support TM in the ISA? (How to evaluate the whole stack) 33

34. Samira Khan University of Virginia Feb 2, 2016 COMPUTER ARCHITECTURE CS 6354 Fundamental Concepts: ISA Tradeoffs The content and concept of this course are adapted from CMU ECE 740