1. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 1 Verilog for Digital Design Chapter 3: Sequential Logic Design

2. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 2 Register Behavior

3. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 3 Register Behavior Sequential circuits have storage Register: most common storage component –N-bit register stores N bits –Structure may consist of connected flip-flops I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst I 2 I 3 Q2Q3Q1Q0 I 1 I 0 Clk 4-bit register D Q R D Q R D Q R D Q R Rst

4. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 4 Register Behavior Vectors Typically just describe register behaviorally –Declare output Q as reg variable to achieve storage Uses vector types –Collection of bits More convenient than declaring separate bits like I3, I2, I1, I0 –Vector's bits are numbered Options: [0:3], [1:4], etc. [3:0] –Most-significant bit is on left –Assign with binary constant (more on next slide) `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst I3I2I1I0 module Reg4(I3,I2,I1,I0,Q3,...); input I3, I2, I1, I0; module Reg4(I, Q,...); input [3:0] I; I: I[3]I[2]I[1]I[0]

5. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 5 Register Behavior Constants Binary constant –4'b0000 4: size, in number of bits 'b: binary base 0000: binary value Other constant bases possible –d: decimal base, o: octal base, h: hexadecimal base –12'hFA2 'h: hexadecimal base 12: 3 hex digits require 12 bits FA2: hex value –Size is always in bits, and optional 'hFA2 is OK –For decimal constant, size and 'd optional 8'd255 or just 255 In previous uses like “A <= 1;” 1 and 0 are actually decimal numbers. ‘b1 and ‘b0 would explicitly represent bits Underscores may be inserted into value for readability –12'b1111_1010_0010 –8_000_000 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst

6. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 6 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule Register Behavior Procedure's event control involves Clk input –Not the I input. Thus, synchronous –"posedge Clk" Event is not just any change on Clk, but specifically change from 0 to 1 (positive edge) negedge also possible Process has synchronous reset –Resets output Q only on rising edge of Clk Process writes output Q –Q declared as reg variable, thus stores value too vldd_ch3_Reg4.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst

7. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 7 Register Behavior Testbench reg/wire declarations and module instantiation similar to previous testbenches Module uses two procedures –One generates 20 ns clock 0 for 10 ns, 1 for 10 ns Note: always procedure repeats –Other provides values for inputs Rst and I (i.e., vectors) initial procedure executes just once, does not repeat (more on next slide) vldd_ch3_Reg4TB.v `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end endmodule

8. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 8 Register Behavior Testbench Variables/nets can be shared between procedures –Only one procedure should write to variable Variable can be read by many procedures Clock procedure writes to Clk_s Vector procedures reads Clk_s Event control "@(posedge Clk_s)" –May be prepended to statement to synchronize execution with event occurrence Statement may be just ";" as in example In previous examples, the “statement” was a sequential block (begin-end) –Test vectors thus don't include the clock's period hard coded Care taken to change input values away from clock edges vldd_ch3_Reg4TB.v `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end endmodule

9. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 9 Register Behavior Testbench Simulation results –Note that Q_s updated only on rising clock edges –Note Q_s thus unknown until first clock edge Q_s is reset to “0000” on first clock edge vldd_ch3_Reg4TB.v... always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end... vldd_ch3_Reg4.v... // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end I_s Q_s time (ns) 102030 40 Clk_s 50 70 000010101111 xxxx000010101111 Rst_s 6080 Remember that Q_s is connected to Q, and I_s to I, in the testbench Initial value of a bit is the unknown value x

10. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 10 Common Pitfalls Using "always" instead of "initial" procedure –Causes repeated procedure execution Not including any delay control or event control in an always procedure –May cause infinite loop in the simulator Simulator executes those statements over and over, never executing statements of another procedure Simulation time can never advance –Symptom – Simulator appears to just hang, generating no waveforms // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s);... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; end time (ns) I_s Q_s 102030 40 Clk_s 50 70 Rst_s 6080

11. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 11 Common Pitfalls Not initializing all module inputs –May cause undefined outputs –Or simulator may initialize to default value. Switching simulators may cause design to fail. –Tip: Immediately initialize all module inputs when first writing procedure // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s);... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end

12. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 12 Common Pitfalls Forgetting to explicitly declare as a wire an indentifier used in a port connection –e.g., Q_s –Verilog implicitly declares identifier as a net of the default net type, typically a one-bit wire Intended as shortcut to save typing for large circuits May not give warning message during compilation Works fine if a one-bit wire was desired But may be mismatch – in this example, the wire should have been four bits, not one bit Unexpected simulation results –Always explicitly declare wires Best to avoid use of Verilog's implicit declaration shortcut `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);...

13. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 13 Finite-State Machines (FSMs)—Sequential Behavior

14. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 14 Finite-State Machines (FSMs)—Sequential Behavior Finite-state machine (FSM) is a common model of sequential behavior –Example: If B=1, hold X=1 for 3 clock cycles Note: Transitions implicitly ANDed with rising clock edge –Implementation model has two parts: State register Combinational logic –HDL model will reflect those two parts Inputs: B; Outputs: X On2On1On3 Off X=1 X=0 B B Combinational logic State register State X B Clk FSM outputs FSM inputs FSM outputs StateNext

15. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 15 Finite-State Machines (FSMs)—Sequential Behavior Modules with Multiple Procedures and Shared Variables Code will be explained on following slides `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule vldd_ch3_LaserTimerBeh.v Inputs: B; Outputs: X On2On1On3 Off X=1 X=0 B B Combinational logic State register State X B Clk FSM inputs FSM outputs StateNext

16. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 16 Finite-State Machines (FSMs)—Sequential Behavior Modules has two procedures –One procedure for combinational logic –One procedure for state register –But it's still a behavioral description `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin... end // StateReg always @(posedge Clk) begin... end endmodule Combinational logic State register State X B Clk FSM inputs FSM outputs StateNext vldd_ch3_LaserTimerBeh.v

17. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 17 `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin... end // StateReg always @(posedge Clk) begin... end endmodule Finite-State Machines (FSMs)—Sequential Behavior Parameters parameter declaration –Not a variable or net, but rather a constant –A constant is a value that must be initialized, and that cannot be changed within the module’s definition –Four parameters defined S_Off, S_On1, S_On2, S_On3 Correspond to FSM’s states –Should be initialized to unique values vldd_ch3_LaserTimerBeh.v

18. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 18 Finite-State Machines (FSMs)—Sequential Behavior Module declares two reg variables –State, StateNext –Each is 2-bit vector (need two bits to represent four unique state values 0 to 3) –Variables are shared between CombLogic and StateReg procedures CombLogic procedure –Event control sensitive to State and input B –Will output StateNext and X StateReg procedure –Sensitive to Clk input –Will output State, which it stores Combinational logic State register State X B Clk FSM inputs FSM outputs StateNext `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin... end // StateReg always @(posedge Clk) begin... end endmodule vldd_ch3_LaserTimerBeh.v

19. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 19 Finite-State Machines (FSMs)—Sequential Behavior Procedures with Case Statements Procedure may use case statement –Preferred over if-else-if when just one expression determines which statement to execute –case (expression) Execute statement whose case item expression value matches case expression –case item expression : statement –statement is commonly a begin-end block, as in example –First case item expression that matches executes; remaining case items ignored –If no item matches, nothing executes –Last item may be "default : statement" Statement executes if none of the previous items matched // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end vldd_ch3_LaserTimerBeh.v

20. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 20 Finite-State Machines (FSMs)—Sequential Behavior Procedures with Case Statements FSM’s CombLogic procedure –Case statement describes states –case (State) Executes corresponding statement (often a begin-end block) based on State's current value –A state's statements consist of Actions of the state Setting of next state (transitions) Ex: State is S_On1 –Executes statements for state On1, jumps to endcase reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end Suppose State is S_On1 Inputs: X; Outputs: B On2On1On3 Off X=1 X=0 B' B vldd_ch3_LaserTimerBeh.v

21. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 21 Finite-State Machines (FSMs)—Sequential Behavior FSM StateReg Procedure –Similar to 4-bit register Register for State is 2-bit vector reg variable –Procedure has synchronous reset Resets State to FSM’s initial state, S_Off... parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext;... // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end... vldd_ch3_LaserTimerBeh.v

22. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 22 Finite-State Machines (FSMs)—Sequential Behavior Modules with Multiple Procedures and Shared Variables Code should now be clear `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule vldd_ch3_LaserTimerBeh.v Inputs: B; Outputs: X On2On1On3 Off X=1 X=0 B B Combinational logic State register State X B Clk FSM inputs FSM outputs StateNext

23. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 23 Finite-State Machines (FSMs)—Sequential Behavior Self-Checking Testbenches FSM testbench –First part of file (variable/net declarations, module instantiations) similar to before –Vector Procedure Resets FSM Sets FSM's input values (“test vectors”) Waits for specific clock cycles –We observe the resulting waveforms to determine if FSM behaves correctly... // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; @(posedge Clk_s); end endmodule vldd_ch3_LaserTimerTB.v B_s X_s time (ns) 102030 40 Clk_s 50 70 Rst_s 6080 90110100

24. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 24 Finite-State Machines (FSMs)—Sequential Behavior Self-Checking Testbenches vldd_ch3_LaserTimerTBDisplay.v // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end B_s X_s time (ns) 102030 40 Clk_s 50 70 Rst_s 6080 90110100 Reading waveforms is error-prone Create self-checking testbench –Use if statements to check for expected values If a check fails, print error message Ex: if X_s fell to 0 one cycle too early, simulation might output: –95: Third X=1 failed

25. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 25 Finite-State Machines (FSMs)—Sequential Behavior $display System Procedure vldd_ch3_LaserTimerTBDisplay.v // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end $display – built-in Verilog system procedure for printing information to display during simulation – A system procedure interacts with the simulator and/or host computer system To write to a display, read a file, get the current simulation time, etc. Starts with $ to distinguish from regular procedures String argument is printed literally... –$display("Hello") will print "Hello" –Automatically adds newline character...except when special sequences appear – %t: Display a time expression –Time expression must be next argument $time – Built-in system procedure that returns the current simulation time –95: Third X=1 failed

26. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 26 Top-Down Design – FSMs to Controller Structure

27. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 27 Top-Down Design – FSMs to Controller Structure Recall from Chapter 2 –Top-down design Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfettered by complexity of creating structure Capture behavior: FSM Capture structure: Controller –Create architecture (state register and combinational logic) –Encode states –Create stable table (describes combinational logic) –Implement combinational logic Capture behavior Simulate W_s P_s S_s K_s Capture structure Simulate W_s P_s S_s K_s Should be the same Combinational logic State register S1S0 N1 N0 X B Clk FSM outputs FSM inputs FSM outputs X=1 X=0 B B' 01 00 1011On2On1 Off On3 Inputs: B; Outputs: X LaserTimer example

28. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 28 Top-Down Design – FSMs to Controller Structure Recall from Chapter 2 –Top-down design Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfettered by complexity of creating structure Capture behavior: FSM Capture structure: Controller –Create architecture (state register and combinational logic) –Encode states –Create stable table (describes combinational logic) –Implement combinational logic X=1 X=0 B B' 01 00 1011On2On1 Off On3 Inputs: B; Outputs: X FSM outputs

29. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 29 Top-Down Design – FSMs to Controller Structure Recall from Chapter 2 –Top-down design Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first, unfettered by complexity of creating structure Capture behavior: FSM Capture structure: Controller –Create architecture (state register and combinational logic) –Encode states –Create stable table (describes combinational logic) –Implement combinational logic X=1 X=0 B B' 01 00 1011On2On1 Off On3 Inputs: B; Outputs: X FSM outputs X = S1 + S0 N1 = S1’S0 + S1S0’ N0 = S1’S0’B + S1S0’

30. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 30 Controller Structure Structural description Test with LaserTimerTB –Same results FSM outputs X = S1 + S0 N1 = S1’S0 + S1S0’ N0 = S1’S0’B + S1S0’ `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 2'b00; reg [1:0] State, StateNext; // State encodings: // S_Off 00, S_On1 01, S_On2 10, S_On3 11 // CombLogic always @(State, B) begin X <= State[1] | State[0]; StateNext[1] <= (~State[1] & State[0]) | (State[1] & ~State[0]); StateNext[0] <= (~State[1] & ~State[0] & B) | (State[1] & ~State[0]); end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule Combinational logic State register S1S0 N1 N0 X B Clk FSM outputs FSM inputs FSM outputs vldd_ch3_LaserTimerStruct.v B_s X_s time (ns) 102030 40 Clk_s 50 70 Rst_s 6080 90110100

31. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 31 Controller Structure Initial state is S_Off –Encoded as "00" –State register set to S_Off during FSM reset Note that CombLogic uses equations, not case statement –Actually CombLogic is still behavioral –Do top-down design again, this time on CombLogic, to get structure FSM outputs vldd_ch3_LaserTimerStruct.v `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 2'b00; reg [1:0] State, StateNext; // State encodings: // S_Off 00, S_On1 01, S_On2 10, S_On3 11 // CombLogic always @(State, B) begin X <= State[1] | State[0]; StateNext[1] <= (~State[1] & State[0]) | (State[1] & ~State[0]); StateNext[0] <= (~State[1] & ~State[0] & B) | (State[1] & ~State[0]); end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule

32. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 32 Common Pitfall: Not Assigning Every Output in Every State FSM outputs should be combinational function of current state (for Moore FSM) Not assigning output in given state means previous value is remembered –Output has memory –Behavior is not an FSM Solution 1 –Be sure to assign every output in every state Solution 2 –Assign default values before case statement –Later assignment in state overwrites default // CombLogic always @(State, B) begin X <= 0; case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end Could delete this without changing behavior (but probably clearer to keep it)

33. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 33 Common Pitfall: Not Assigning Every Output in Every State Solution 2 –Assign default values before case statement –Later assignment in state overwrites default –Helps clarify which actions are important in which state –Corresponds directly to the common simplifying FSM diagram notation of implicitly setting unassigned outputs to 0 TS A=0 B=1 C=0 A=0 B=0 C=1 TS B=1C=1 case State S: begin A <= 0; B <= 1; C <= 0; end T: begin A <= 0; B <= 0; C <= 1; end endcase A <= 0; B <= 0; C <= 0; case State S: begin B <= 1; end T: begin C <= 1; end endcase

34. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 34 More Simulation Concepts

35. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 35 The Simulation Cycle Instructive to consider how an HDL simulator works –HDL simulation is complex; we'll introduce simplified form Consider example SimEx1 –Three reg variables – Q, Clk, S –Three procedures – P1, P2, P3 Simulator's job: Determine values for nets and variables over time –Repeatedly executes and suspends procedures Note: Actually considers more objects, known collectively as processes, but we'll keep matters simple here to get just the basic idea of simulation –Maintains a simulation time Time `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule vldd_ch3_SimEx1.v

36. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 36 The Simulation Cycle Start of simulation –Simulation time Time is 0 –Bit variables/nets initialized to the unknown value x –Execute each procedure In any order, until stops at a delay or event control `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule vldd_ch3_SimEx1.v Q Clk S Variables x x x Start x 0 x 0 Time (ns): P1 P2 P3 Clk <= 0, then stop. Activate when Time is 0+10=10 ns. No actions, then stop. Activate when S changes. No actions, then stop. Activate when Clk changes to 1 Procedures We'll use arrow to show where a procedure stops

37. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 37 The Simulation Cycle Simulation cycle –Set time to next time at which a procedure activates (note: could be same as current time) In this case, time = 10 ns (P1 activates) –Execute active procedures (in any order) until stops vldd_ch3_SimEx1.v Q Clk S Variables x x x Start x 0 x 0 Time (ns): x 1 x 10 P1 P2 P3 Activate when Time is 10 ns. Activate when S changes. Activate when Clk changes to 1. Procedures Clk <= 1, stop, activate when Time=10+10=20 ns. `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule

38. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 38 The Simulation Cycle Simulation cycle –Set time to next time at which a procedure activates Still 10 ns; Clk just changed to 1 (P3 activates) –Execute active procedures (in any order) until stops vldd_ch3_SimEx1.v Q Clk S Variables x x x Start x 0 x 0 x 1 x 10 x 1 1 Time (ns): P1 P2 P3 Activate when Time is 20 ns. Activate when S changes. Activate when Clk changes to 1 Procedures S <= 1, stop, activate when Clk changes to 1 again `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule

39. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 39 The Simulation Cycle Simulation cycle –Set time to next time at which a procedure activates Still 10 ns; S just changed (P2 activates) –Execute active procedures until stops vldd_ch3_SimEx1.v Q Clk S Variables x x x Start x 0 x 0 x 1 x 10 x 1 1 0 1 1 Time (ns): P1 P2 P3 Activate when Time is 20 ns. Activate when S changes. Activate when change on Clk to 1. Procedures Q <= 0 (~S), stop, activate when S changes. `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule

40. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 40 The Simulation Cycle Simulation cycle –Set time to next time at which a procedure activates In this case, set Time = 20 ns (P1 activates) –Execute active procedures until stops vldd_ch3_SimEx1.v Q Clk S Variables x x x Init x 0 x 0 x 1 x 10 x 1 1 0 1 1 Time (ns): P1 P2 P3 Activate when Time is 20 ns. Activate when S changes. Activate when change on Clk to 1. Procedures Clk <= 0, stop, activate when T=20+10=30ns. 0 0 1 20 `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule

41. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 41 The Simulation Cycle Simulation ends when user-specified time is reached Variable/net values translate to waveforms vldd_ch3_SimEx1.v Q Clk S Variables x x x Init x 0 x 0 x 1 x 10 x 1 1 0 1 1 Time (ns): 0 0 1 20 0 1 1 30 0 1 0 1 1 0 1 0 0 40 1 1 0 50 Q Clk S Variables Time (ns) 102030 40 500 x x `timescale 1 ns/1 ns module SimEx1(Q); output reg Q; reg Clk, S; // P1 always begin Clk <= 0; #10; Clk <= 1; #10; end // P2 always @(S) begin Q <= ~S; end // P3 initial begin @ (posedge Clk); S <= 1; @ (posedge Clk); S <= 0; end endmodule

42. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 42 Variable Updates Assignment using "<=" ("non blocking assignment") doesn't change variable's value immediately –Instead, schedules a change of value by placing an event on an event queue –Scheduled changes occur at end of simulation cycle Important implications –Procedure execution order in a simulation cycle doesn't matter Assume procedures 1 and 2 are both active –Proc1 schedules B to be 1, but does not change the present value of B. B is still 0. –Proc2 schedules A to be 0 (the present value of B). –At end of simulation cycle, B is updated to 1 and A to 0 –Order of assignments to different variables in a procedure doesn't matter Assume C was 0. Scheduled values will be C=1 and D=0, for either Proc3a or Proc3b. –Later assignment in procedure effectively overwrites earlier assignment E will be updated with 0, but then by 1; so E is 1 at the end of the simulation cycle. Simulation cycle (revised) –Set time to next time at which a procedure resumes –Execute active procedures –Update variables with schedule values Assume B is 0. Proc1: B <= ~B; Proc2: A <= B; A will be 0, not 1. Proc3a: C <= ~C; D <= C; Proc3b: D <= C; C <= ~C; Same Proc4: E <= 0;... E <= 1; Recall FSM output assignment example, in which default assignments were added before the case statement.

43. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 43 Resets

44. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 44 Resets Reset – Behavior of a register when a reset input is asserted Good practice dictates having defined reset behavior for every register Reset behavior should always have priority over normal register behavior Reset behavior –Usually clears register to 0s –May initialize to other value e.g., state register of a controller may be initialized to encoding of initial state of FSM Reset usually asserted externally at start of sequential circuit operation, but also to restart due to failure, user request, or other reason `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst

45. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 45 Rst Clk Q I xxxx Synchronous Reset Previous examples used synchronous resets –Rst input only considered during rising clock `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst Rst=1 has no effect until rising clock

46. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 46 Rst Clk Q I xxxx Asynchronous Reset Can also use asynchronous reset –Rst input considered independently from clock Add "posedge Rst" to sensitivity list `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk, posedge Rst) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4AsyRst.v I3I2I1I0 Q3Q2Q1Q0 reg(4) Rst Clk Q I Asynchronous reset Synchronous reset Rst=1 has almost immediate effect Rst=1 has no effect until next rising clock

47. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 47 Asynchronous Reset Could have used asynchronous reset for FSM state register too... // StateReg always @(posedge Clk, posedge Rst) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end... vldd_ch3_LaserTimerBehAsyRst.v... // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end... Synchronous Asynchronous

48. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 48 Synchronous versus Asynchronous Resets Which is better – synchronous or asynchronous reset? –Hotly debated in design community Each has pros and cons –e.g., asynchronous can still reset even if clock is not functioning, synchronous avoids timing analysis problems sometimes accompanying asynchronous designs We won’t try to settle the debate here –What’s important is to be consistent throughout a design All registers should have defined reset behavior that takes priority over normal register behavior That behavior should all be synchronous reset or all be asynchronous reset –We will use synchronous resets in all of our remaining examples

49. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 49 Describing Safe FSMs

50. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 50 Describing Safe FSMs Safe FSM – If enters illegal state, transitions to a legal state Example –Suppose example has only three states –Two-bit encoding has illegal state encoding "11" Also known as "unreachable" state Not possible to enter that state under normal FSM operation But actually possible to enter that state due to circuit error – e.g., electrical noise that causes state register bit to switch X=1 X=0 B B' 01 00 10On2On1 Off Inputs: B; Outputs: X

51. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 51 Describing Safe FSMs Safe FSM – If enters illegal state, transitions to a legal state Example –Suppose example has only three states –Two-bit encoding has illegal state encoding "11" –Safe implementation Transition to appropriate legal state Even though that undefined state appears to be unreachable Thus, FSM recovers from the error X=1 X=0 B B' 01 00 10On2On1 Off Inputs: B; Outputs: X X=0 11

52. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 52 Describing Safe FSMs in VHDL Unsafe FSM description –Only describes legal states, ignores illegal states Some synthesis tools support "safe" option during synthesis –Automatically creates safe FSM from an unsafe FSM description... reg [1:0] State, StateNext; always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_Off; end endcase end...

53. Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 53 Describing Safe FSMs in VHDL Explicitly describing a safe FSM –Include case item(s) to describe illegal states –Can use "default" case item Executes if State equals anything other than S_Off, S_On1, or S_On2 Note: Use of default is wise regardless of number of states –Even if number is power of two, because state encoding may use more than minimum number of bits e.g., one-hot encoding has many more illegal states than legal states Note: If synthesis tool support "safe" option, use it –Otherwise, tool may automatically optimize away unreachable states to improve performance and size, but making state machine unsafe... reg [1:0] State, StateNext; always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_Off; end default: begin X <= 0; StateNext <= S_Off; end endcase end... vldd_ch3_LaserTimerBehSafe.v