1. W.J.E.C. Electronics ET4 – Communication Systems Solutions to Sample Questions Jan 2010

2. Question 1. 1. The following graphs show different ways in which Pulse Code Modulation can be used in a communication system. For each case state i) which method is being used, either PPM, PWM or PAM. ii) sketch the original signal which the PCM output represents.

3. Question 1. a)(i) Type of PCM used.................................. time Amplitude time (ii) Draw a possible modulating signal below Amplitude Pulse Width Modulation (1) (2) (1) (0)

4. Question 1. b)(i) Type of PCM used.................................. time Amplitude time (ii) Draw a possible modulating signal below Pulse Position Modulation (1) (1) (2) (0) (1) Amplitude time

5. Question 2. 2. The ASCII code is an internationally agreed method of coding alphanumeric characters in computer systems. Character ASCII Code 10110001 20110010 30110011 40110100 50110101 60110110 70110111

6. Question 2. a)A computer system uses odd parity. Start, stop and parity bits have to be added before the signal can be transmitted. i.What is the purpose of the start bit ? ………………………………………………………………….. [1] ii.What is the purpose of the parity bit ? ………………………………………………………………….. [1] The start bit informs the receiving equipment that a data packet is about to follow by taking the data line to logic 0 The parity bit is used to indicate if there is a single error in the received data / simple form of error-checking.

7. Logic 1 Logic 0 Voltage time Question 2. b)The graph below shows the signal for a numeric character, received at the end of the transmission link. i)Label the start, stop, data and parity bits. [4] ii)Using the table above, determine what numeric character was transmitted to the receiver. …………………[1] Data Bits Parity bit Stop Bit Start bit 3

8. Logic 1 Logic 0 Voltage time Question 2. c)The same character was transmitted again, and the information received is shown in the graph below. i)What character has now been received ? ………………… [1] 0 1 1 0 1 1 0 6

9. Question 2. ii)Given that an attempt was made to transmit the same character, as in part (b). Explain why the receiving equipment would not have rejected the data as being incorrect. ………………………………………………………… [1] There are two errors in the data, the simple parity check still passes because there are still an odd number of logic 1’s in the data so no error is detected.

10. Question 2. iii)Describe how this situation can be avoided by using a multiple bit parity system. ……………………………………………………….. [3] Description of a multiple bit parity system (1) Table showing how parity bits assigned (1) Description of how an error is detected (1) i.e. 2 / 4 or 5 bit system as no of bits not specified.

11. Question 3. 3. a.The superheterodyne radio receiver offers improved selectivity and sensitivity compared to the simple radio. Complete the following block diagram of the superheterodyne receiver. [4] Tuned RF Amp Local Oscillator A.F. Amp Mixer

12. Question 3. 3. b. What type of filter is the IF Filter. ………………………………………………………. [1] c.The following circuit shows an I.F. filter with a resonant frequency of 500 kHz connected to a signal generator with V IN set to 6V. V IN is kept at 6V and the frequency increased to give the maximum value of V OUT. 20kΩ C 1.0 mH r L =.......Ω V IN V OUT Bandpass Filter

13. Question 3c. (i)V OUT must be a maximum at a frequency of 500 kHz. Calculate the value of C that will cause resonance to occur at a frequency of 500 kHz. ………………………………………………………. [2]

14. Question 3c. (ii)The bandwidth of the filter should be 10 kHz. Calculate the Q-factor of the circuit.. ………………………………………………………. [2]

15. Question 3c. (iii)Hence calculate the value of r L. ………………………………………………………. [2]

16. Question 3d. (d)(i) Calculate the Dynamic Resistance R D of the filter ………………………………………………………. [2]

17. Question 3d. (d)(ii)Use your answer to part (d)(i) to determine the maximum value of the voltage V OUT with V IN set to 6V. ………………………………………………………. [2]

18. (e)Sketch the frequency response of the filter using the axes below. Label all important values. [2] Question 3e. 480 490 500 505 510 freq / kHz V OUT 64206420 5.32V 0.7x5.32 = 3.72V Bandwidth=10kHz

19. Question 4. 4. a) A good quality transmission system uses a four bit parity system, with the parity bits assigned to the data bits in accordance with the following table. D7D7D7D7 D6D6D6D6 D5D5D5D5 D4D4D4D4 D3D3D3D3 D2D2D2D2 D1D1D1D1 D0D0D0D0 P3P3P3P3 P2P2P2P2 P1P1P1P1 P0P0P0P0 xxxxx xxxxx xxxxx xxxxx

20. Question 4a. The following data is to be transmitted along a transmission line. D7D0 1 0111010 Determine the values of the parity bits P3 - P0 that should be transmitted after this data for an odd parity system. P3 =............ P2 =........... P1 =........... P0 =............ [2] 1 0 0 1

21. Question 4b. The following data and parity bits are received from a transmission line of a system using even parity. D7 D0 P3 P0 1 1 1 0 1 0 1 1 0 0 1 0 There is a single error in the received data. (i)By careful consideration of the received data, determine where the error is located and therefore write down the correct version of the received data. [2]     D7D7D7D7 D6D6D6D6 D5D5D5D5 D4D4D4D4 D3D3D3D3 D2D2D2D2 D1D1D1D1 D0D0D0D0 P3P3P3P3 P2P2P2P2 P1P1P1P1 P0P0P0P0 111010010010

22. Question 4b. (ii)Explain how you have determined the location of the error. ………………………………………………………. [1] Parity bits P 0, P 2 and P 3 are all wrong. These three parity bits are only common to D 1. Therefore it is D1 that contains the error and should be a logic 0, and not a 1 as shown.

23. Question 4c. The following data and parity bits are received from a transmission line of a system using even parity. D7 D0 P3 P0 0 0 1 1 0 0 1 0 0 1 0 0 There is a single error in the received data. (i)In this case the received data cannot be reconstructed with any certainty. Use the information provided in the received data to explain why this is the case. [2]    

24. Question 4b. (i)In this case the received data cannot be reconstructed with any certainty. Use the information provided in the received data to explain why this is the case. ………………………………………………………. [1] Parity bit P 0 is the only parity bit to fail. however because D 3 is only paired with P 0, it is impossible to decide if it is D 3 or P 0 which contains the error, correction is not possible.

25. Question 4b. (ii)Explain how the system could be modified to ensure that this problem did not occur in the case of a single error in the received data. ………………………………………………………. [1] An extra parity bits P 4 is required making 5 parity bits in total. (1) The extra parity bit is determined by grouping D 7, D 6, D 3 and D 2 together. (1)

26. Question 5. 5. The following block diagram shows a Pulse Code Modulation (PCM) Transmitter.. Low Pass Filter Sampling Gate 11 bit A.D.C. P.I.S.O. Shift Register Clock B Clock A Input Output

27. Question 5. a)What is the purpose of the low pass filter in the PCM Transmitter. ………………………………………………………. [1] The low pass filter cuts out the high frequency parts of the input signal, so that none of these frequencies are passed to the sampling circuit otherwise aliasing errors can occur during reconstruction at the receiver.

28. Question 5. b)The PCM transmitter shown above is to be used for transmitting speech information. The following diagrams show three possible Low Pass Filter Circuits.

29. Question 5b. i)By calculation, determine which filter would be the most appropriate to use for the PCM transmitter. ………………………………………………………. [2] Circuit Chosen = B A B C

30. Question 5. ii)Justify your decision, by explaining why you have chosen the filter circuit in part (i) ………………………………………………………. [1] In Circuit A the break frequency is too high for a speech signal. Circuit C has a break frequency which is too low, as it is less than 1kHz and so conversations would be badly distorted. Circuit B has sufficient bandwidth for speech.

31. Question 5c. (i)Suggest a suitable frequency for Clock A based on your answer to (b) ………………………………………………………… [1] (ii) Justify why you have chosen your answer to (c)(i) ………………………………………………………. [2] Minimum freq = 2 x 3526 = 7052Hz,  8kHz Nyquist sampling theorem states that sampling frequency must be a minimum of 2x the highest frequency present to enable reconstruction. (1) 8kHz allows a small tolerance to prevent aliasing (1).

32. Question 5d. For the system, the Analogue to Digital Converter (ADC) has an input voltage range of 0 to 8V. i)how many voltage levels are provided by the ADC ? ………………………………………………………. ……………………………………………………….[1] ii)What is the resolution of the system ? ………………………………………………………. [1]

33. Question 5e. Clock B must operate at a higher frequency than Clock A for the system to work properly. Explain why this is the case. ………………………………………………………. [1] Clock B drives the PISO shift register, which has to output all 11 bits of the digital code, before the next sample is taken by the sampling gate. Clock B must operate at least 11 times faster than Clock A.

34. Question 5f. In the space below draw a block diagram of a suitable PCM Receiver using the following functional blocks. low pass filter SIPO clock DAC SIPO shift register Schmitt trigger [3] Low Pass Filter SIPO Clock DAC SIPO Shift Register Schmitt Trigger

35. Any Questions ?