1. Zynq-7000 All Programmable SoC for Smarter Vision
Time on foil: 1mins
Speaker Notes: Main:
There have been many changes across Xilinx over the past few years such as our Value Added Leadership, A Generation Ahead, Smarter Networks and now Smarter Vision.
So about a month ago we launched the “A Generation Ahead For Smarter Networks” campaign. On April 8th, last Monday, the “A Generation Ahead For Smarter Vision” campaign was launched on Xilinx’s website.
Key Take-a-way:
Objective of slide:
Dec, 2013

2. The First All Programmable SoC
Production: NOW
4,000+ Zynq DevKits Purchased
500+ unique customers actively designing
100+ AP SoC specific partners
All Major OS’s supported and in use
20+ different development boards
Won every award at every event entered
2012
2010
Time on foil: 2mins
Speaker Notes: Main:
What we have is the Perfect Platform for Smarter Vision and we call it Zynq.
It is the optimal combination of Software Programmability, Hardware Programmability and I/O Programmability all in on silicon device to enable all these applications.
We have everything from Driver’s Assistance and Machine Vision to Broadcast Reference Monitors and Digital Cinema projectors to Medical Displays and A&D UAV’s. In fact we have rolled up almost 30 different applications that Zynq is a good fit. On the website we have highlighted 11 of these design examples for you to use with customers.
So how does it compare to other solutions in the market?
Key Take-a-way:
Objective of slide:

3. Xilinx Pioneered the All Programmable SoC
Innovation with All Programmable SoC
Innovated a new class of all programmable SoC devices
Executed by delivering tools, samples and enabling eco-system
Momentum from first shipment, delivering boards, customer wins
Safe choice with a comprehensive offering already in existence today
ARM
Partnership
(AXI-4)
First Customer Shipment
1st Zynq based product delivered by Customer
Production
Availability
Security & Safety
Enablement
Zynq Product Announcement
OS & Tools
Architecture
Announcement
Time on foil: 2mins
Speaker Notes: Main:
What we have is the Perfect Platform for Smarter Vision and we call it Zynq.
It is the optimal combination of Software Programmability, Hardware Programmability and I/O Programmability all in on silicon device to enable all these applications.
We have everything from Driver’s Assistance and Machine Vision to Broadcast Reference Monitors and Digital Cinema projectors to Medical Displays and A&D UAV’s. In fact we have rolled up almost 30 different applications that Zynq is a good fit. On the website we have highlighted 11 of these design examples for you to use with customers.
So how does it compare to other solutions in the market?
Key Take-a-way:
Objective of slide:
2010
2011
2012
2013
Emulation Platform
Demonstrated and delivered
Open Source Linux
Public Push
Dev. Boards Available
1 GHz Peak Processing Performance
Segment
Solutions

4. The Best All Programmable Platform for Smarter Vision
Strong Analytic, Protocol Stacks and System Management
Massive Parallel FPGA Processing
Most Optimized Interconnect
Unprecedented Levels of High Performance and Low Power
Enable Smarter Vision Designs
Main Messages:
We made sure that we designed the most efficient interface between the ARM System and the FPGA Fabric so people could benefit from the conjoint value of the massive parallel processing of the FPGA Fabric for high performance processing functions with the power of the ARM architecture for analytics and control functions.
This interface was a lot more than putting a fat pipe of data between the 2 domains (128bit I/F like Altera has implemented in their SoC FPGA) but looking at the use cases and finding the right balance between performance, latency and routability within the FPGA.
Combined with the SmartCORE IP solutions from Xilinx, Zynq enables applications that were not possible before such as Vision and wireless applications, but also greatly improves the efficiency of many applications in a lot of domains such as broadcast, Consumer, Aerospace & Defense, Industrial, Medical, Surveillance, Automotive, Wired and Wireless.
Note about this slide:
The link to the “Most Optimized Interconnect” box will take you to a slide that will explain how our PS to PL architecture is superior to the way Altera implemented it in SoC FPGA
The link at the bottom of the slide, will take you to:
Simple examples of Smarter Vision and Smarter Networks in the General Zynq Gen Ahead presentation
Market specific examples in the segment Zynq Gen Ahead presentation
Possible Questions:
Some questions may arise as to why this combination and the way Xilinx did it enables applications not possible before with 2 chips.
Although this is part of the Zynq introduction, the simple answer is that certain applications require both, massive Parallel signal processing and complex Analytics and Control, such as Wireless and Vision applications. Now these applications also require a large amount of data sharing between the “processing” and “Analytics/control” domain and although this may sometimes be possible with 2 chip solutions, the performance limitation going between the 2 chips and especially the power needed to do the interface would make a 2 chip solution not a viable one.
What about Arria X SoC?:
From what we can see it does not look like Altera has changed their FPGA to HPS interfacing. They still rely on a single wide 128bit bus, so the messages here stil apply.
One thing that Altera seem to have changed is the way they connect the ACP port to the fabric but Altera is remaining too vague for us to know if this is just a way to position their product or if they did indeed change their ACP implementation.

5. Zynq HW Architecture CPU Subsystem I/O Peripheral Memory Control Hub
Programmable Logic

6. Zynq-7000 AP SoC Family Overview
Device Tables
Programmable Logic

7. The CoreMark® Performance Leader Compared to other Cortex-A9 MPCore devices
Presenter notes:
This slide highlights that despite the fact that Zynq is the first ARM based SoC that Xilinx offers, our architecture team did a fantastic job showing that we know how to integrate the ARM core, as well, if not better, than anybody else as we are showing on this slide that we lead the other Dual core 1GHz architecture with our 1GHz dual core Zynq.
Goal is not really to brag about it as mopst players are on par, but really to show that any customer who may think that other guys such as TI and Freescale know better how to build ARM based SoC can see here that this is NOT the case.
It is important to also note that 7020 numbers are now even higher since we have upgraded the performance to 866MHz
Pure SW performance better than other comparable Cortex-A9 based devices

8. Processing System Benchmark Proven Results Z-7020 vs
Processing System Benchmark Proven Results Z-7020 vs. Cyclone V SoC with SPEC® CPU2000 Benchmarks
66%
Device
CPU
MHz
DDR3
Width
ECC
5CSXD6
925
400
32b No
Z-7020
866
533
Xilinx Advantage
Up to 66% performance advantage on memory intensive tests.
12% average performance advantage combining all the results
Even greater advantage at lower speed grades
12%
Main Messages:
Altera has been claiming that their implementation of the Dual Core Cortex-A9 is better than Zynq’s and that their memory architecture is superior to the one we developed for Zynq.
To find out which PS implementation is indeed better we ran a series of benchmarks: the SPEC CPU 2000 consists of 24 benchmarks divided into an integer group and a floating point group
To make it a fair comparison we did not compare 7045 with Cyclone V SoC but the 7020 since, on the paper those devices look comparable
Several tests were ran including tests where we actually ran Zynq and Cyclone V SoC at the exact same frequency (CPU and DDR) and even in this mode Zynq was faster.
More details on all the tests are available on the SouRCe in the SoC competitive central.
In this Gen Ahead presentation there is also a comparison with ECC that demonstrates that despite the fact that Cyclone V SoC supports 32b ECC externally, Zynq actually still offers a 11% higher performance when used with 16b ECC external memories compared to Cyclone V SoC with 32b DDR external interface.
On this slide we show the faster speedgrade, and we see that despite Cyclone V SoC processors running at 925MHz, Zynq performance is actually significantly higher (up to 66% for memory intensive tests and on average 12% faster when you take the GeoMean of all the benchmark results.
Other benchmarks with slower speedgrades are available on the SouRCe but it is important to note that these benchmarks are actually better. Reason for this is that, as the slowest speedgrade Zynq has higher CPU frequency (667MHz vs. 600MHz) and while Zynq maintains 533MHz DDR3 performance, Cyclone V SoC sees its DDR3 performance reduce to 333MHz. Because of this at slow speedgrades the CPU2000 benchmarks show greater than 20% performance advantage for Zynq.
The take away from this is that processor frequency is only 1 element of the Processor performance and that many other architectural elements play an important role. This benchmark also shows that Altera’s architecture is significantly limited by the external DDR performance.
Altera uses the processor MHz to claim that they offer the “Industry’s highest performance SoC”, and we are confidently encouraging our customers to run their own benchmark that this is a completely false claim, and that is the clear leader in performance.
Note about this slide:
The Geomean value represented here is actually the midpoint between integer benchmarks and floating points benchmarks. For specific results on Integer and Floating Point results, please take a look at the supportive slides by clicking on the link.
Possible Questions:
Yes but I am using ECC and Cyclone V SoC supports 32b and Zynq only supports 16b, so this benchmark is not for me.
In this deck there is also a comparison with ECC enabled, and despite the fact that Zynq only supports 16b ECC the benchmarks show an average of 15% higher performance with Zynq compared to Cyclone V SoC.
What about Arria 10 SoC?:
As this related to an actual benchmark and not a paper measurement, and since Arria 10 SoC is many many months away from first sample, there is no point using Arria 10 SoC for comparison.
Altera Advantage
24 CPU2000 relative test results
High Processor Performance despite lower MHz.

9. The Truth About Memory Bandwidth
Back
The Truth About Memory Bandwidth
Memory BW from FPGA through PS is limited by external memory controller
Important to have at least 1066Mbps for 1080p60 Video
1333 Mbps expands BW as needed for Higher Performance OS Apps
Artix-7 based Zynq have 34% MORE memory bandwidth than Cyclone-V SoC
Artix-7 based Zynq have the SAME overall memory bandwidth as more expensive Arria-V SoC
Kintex-7 based Zynq have 23% MORE memory bandwidth than Arria-V SoC
GAP
Bandwidth
Arria V SoC
4.3 GB/s
5.3 GB/s
Cyclone V
SoC
23%
4.3 GB/s
34%
1333 Mbps
1066 Mbps
3.2 GB/s
Zynq
7000 (Artix based)
Zynq
7000 (Kintex based)
1066 Mbps
800 Mbps
All bandwidth numbers are theoretical Maximum

10. Zynq-7000 Safety and Security
Back
Zynq-7000 Safety and Security
Safety and security are addressed across every system element and every operational phase
Hardware
Anti-tamper
Trust
Information Assurance
Secure System Boot
ROM Code
Boot loader
OS Image
Security & Safety require a holistic approach
Zynq-7000 AP SoC must address traditional FPGA safety and security requirements
Zynq-7000 AP SoC must also address safety and security during System Boot and Software Execution
Similar to all other platforms for embedded products
Advanced start-up and fall-back scenarios
Secure software start-up
Concurrent execution of real-time and general purpose tasks
Isolation of security-sensitive data
Support for safe and secure RTOS
Safety
Run-time assurance
Security
Protect hardware, software and data from tampering or copy
Traditionally an Aerospace & Defense challenge
UAV, Cryptography, …
Increasingly critical in most applications:
Automotive driver assistance
Industrial factory automation
Surveillance
Medical imaging
Consumer products
Wired communication
Wireless communication
Software Execution
Protect real-time applications
Protect secure processes & data
Isolate accelerators & IP cores

11. Zynq-7000 Hardware Security
Back
Zynq-7000 Hardware Security
Security-Related Features
AES-256 Encryption (BBRAM key)
AES-256 Encryption (eFUSE key)
Secure Config/Boot (PL/PS)
Hardened Readback Disable
HMAC Bitstream Authentication
FSBL RSA-2048 Authentication
ARM TrustZone support of Processing System
ARM TrustZone support of Programmable Logic
SEU Checker
JTAG Disable/Monitor
Internal Keyclear
Internal Config Mem Clear
On-chip Temp/Volt Monitoring
PROG_B Intercept
Unique Identifier (Device DNA)
Unique Identifier (User eFUSE)
Xilinx applies years of hardware security IP to Zynq-7000
Software-configurable hardware (i.e. Zynq-7000 programmable logic) must be Trusted at instantiation and run-time
Anti-tamper
Trust
Information Assurance
Encryption, authentication, key storage, physical environment sensors, and device-identifiers capabilities

12. Zynq-7000 Secure Boot – The Basics
Cryptographic Service
Implementation
SW FSBL SW
User App
Firmware PL Bitfile
Confidentiality
256-bit AES/CBC w/ volatile & non-volatile key
Yes
Symmetric Authentication
HMAC (SHA-256)
Asymmetric Authentication
RSA-2048
N/A
Integrity
HMAC (SHA-256) and CRC
Zynq-7000 provides the user the ability to boot securely from the moment power is applied

13. Most Reliable AP SoC Product in the Market
Higher Perf. System with ECC
Advanced and Transparent SEU testing
Unique FPGA SEU Mitigation
Outstanding FIT results
Most Reliable AP SoC Product in the Market
GAP
< 312
~1725
MTBF
(Mean Time Between Failure calculated in 1000 hours for SoC device)
Xilinx
Complete system approach to reliability
Best external DDR performance with ECC
Thermal reliability with XADC technology
Main Messages:
Now reliability is also an interesting beast where Zynq has a significant advantage over SoC FPGA
One cannot look at reliability from just a single element and reliability needs to be looked at in all aspects at the system level.
There are 3 main elements to reliability:
Making sure that when interfacing with External memories the device can reliably read the data coming from the memory and correct any error that may be presented to it. For this Zynq offers 16bit ECC interface on the PS DDR controller which actually offers to the processors higher performance than the 32bit ECC that SoC FPGA offers. Xilinx has benchmarks to show this.
Having the highest kevel of immunity to SEU in the device itself. For this, one cannot look simply at the Processing System but needs to look at the overall device FIT rate and Zynq has a 5x better FIT rate (or MTBF) than SoC FPGA. This is coming from the fact that the FPGA FIT rate of the Xilinx FPGA are far superior to the Altera FPGAs and also because we offer the SEM IP which considerably reduces FPGA FIT.
Lastly there is a 3rd element which is Thermal reliability, and XADC enables the capability to carefully monitor the temperature of the device which enables the building of systems with higher thermal reliability
All in all when you combine external ECC advantage, the better overall FIT rate on the entire device and the thermal reliability Zynq is definitely a generation ahead of SoC FPGA to build reliable systems.
Note about this slide:
FIT represents the Failure in time and represent the number of failure due to SEU on a device over a certain period of time
MTBF = 1/FIT and represents “Mean Time Between Failures” and is the average time between 2 failures on a given device
Xilinx is leading the way in SEU testing and reporting. Some of this comparison is based on what we have heard from customers as Altera does not publish FIT rate numbers …
Just this shows that Altera is not confident in the numbers or are not proud of them
You should ask your customer to not take what we say for granted and ask Altera to show them the number and make that assessment by themselves.
Clicking on the links will give you the extra level of details on the reliability aspects
Possible Questions:
What about Arria X SoC?:
Not much changes, except a wider 64bit w/ECC memory interface available in the larger device in 1 given package.
The Zynq message on external reliability is going to be reduced given that Arria 10 SoC is also planned to have faster external memory performance.
For internal reliability, they will still face issues with their derived die strategy and more sensitive FPGA design.
Arria 10 SoC does not seem to have any built in ADC so Thermal reliability is still going to be a challenge for them.
Altera
Performance limited with no FPGA ECC solution
Derived die strategy considerably impacts reliability
No Thermal reliability solution

14. Proven Productivity All Programmable Abstractions and Automation
Industry leading high-level synthesis
C, C++, SystemC, IP-based design
MathWorks, National Instruments
Comprehensive Software Tools
Free SDK from Xilinx
Full support for ARM DS-5 tool chain
All major software tools supported
Main Messages:
The last elements that puts Zynq a generation ahead of competing solutions is the way Xilinx has put the emphasis in improving productivity for its customers so you can benefit from improved Time to Market and especially Time to Revenue.
First looked at the challenges that FPGA designers face when designing with FPGAs but also the designers who are looking at designing with Zynq. And for that we introduced the All Programmable Abstraction concept which represents the elements that we and some of our partners have developed to enable development and design with high level languages such as C, C++, …
Secondly, there are many SW tools available for the ARM Cortex A9 and many reason to select one over the other. From Day 1 Xilinx recognized these wide spread needs and did not want to force its customer into a use model, so we are offering a large selection to our customers
And lastly, We also wanted to make sure that we could get you up and running with your design as quickly as possible and we worked internally and also with our partners to make sure that you had the foundations needed to concentrate on your value add when developing your application
Needless to say that Zynq being available in full production now is the #1 time to market advantage. You can get started with confidence.
Note about this slide:
Possible Questions:
What about Arria 10 SoC?:
These messages are strengthening for Zynq when compared to Arria 10 SoC, as the ready to use solutions for Zynq are there and available (boards, SOM, IPs, Segment TDPs) while Arria 10 is not an available product so for example it does not have any board to be developed with.
The All Programmable Abstraction message continues to strengthen with IPI, Vivado HLS, and announcements from partners for Abstraction tools and will not be affected by Altera’s Silicon strategy and execution.
Ready to Use Solutions
>20 boards and SOM available
Large Selection of AXI-based IPs
Many segment solutions readily available

15. Parallel Developments of your AP SoC Based Application
Software Developments
Hardware Developments
Processor boots first like any ARM based SoC.
SW developers can use their favorite SW tool to load / debug SW code over JTAG
Programmable Logic patiently waiting for configuration
Reference SW boots processor first leaving PL up and ready to be programmed through JTAG
Vivado Probe connects to Programmable Logic like to any other FPGA
FPGA developer can start loading / debug like for any FPGA
Main Messages:
This slide is here to show that SW and HW designers can independently develop and debug their portion of the design without requiring intervention of the other “side”:
For SW developers, the Zynq device boots like any other ARM processor and the SW developers are free to use any of their favorite Debug tool. They do not have to worry about the Programmable Logic portion as the Zynq tools, when creating the final bootloader automatically configure the Programmable Logic to patiently wait for configuration. If not configuration is provided, the Programmable Logic keeps on waiting, while the SW developer can run and debug its code in a completely autonomous way.
 For a SW developer it is like developing code on any standard ARM based microprocessor.
For HW designers, the Zynq Tools create the necessary bootloader to configure the Programmable Logic with the designer’s FPGA design and puts the ARM cores in a No-Operation state, leaving the FPGA designer to debug its Programmable Logic code without having to pay attention to what the processor cores are doing.
 For a HW designer it is like designing HW on any Xilinx FPGA.
Note about this slide:
This slide is here to address Altera’s claim to our customers that designing with Zynq is complicated for an FPGA designer because the FPGA does not boot on its own.
It is obvious that Altera is trying to use their dual boot method to spread some FUD about Zynq stating that you need a SW expert to be able to design with Zynq (even the FPGA portion).
This is untrue as we provide the basic necessary code for a designer to boot the processor in a wait and see mode, while the FPGA designer can work on debugging its FPGA design.
Possible Questions:
SW developments like any other
ARM based SoC
HW developments like any other
Xilinx FPGA

16. Widest Selection of Software and Tools
SDK
Main Messages:
So as mentioned earlier, we realized quickly that when it comes to SW Tools different users have different requirements and many want to keep the tool that they are familiar with as it brings enhanced productivity to them.
We also realized that is often a cost aspect which is non negligible, and we wanted to make sure that we would have a free solution.
This not only reduces the cost of development, but also enables more people to work in parallel with the SDK tools and improve time to market
Obviously we have complete support for the ARM DS-5 and have actually shows DS-5 demo working as early as October 2011 (2 months before we had silicon using the Emulation Platform)
But in addition we also realize that there may be a few other popular Tools that you may want to use, and we have support for the main ones.
In essence, this offering gives the possibility to large designs team to do most of the work with the Xilinx SDK and not have to pay for seats that are being used, and use some of the commercial tools for certain aspects of the development or debug.
Note about this slide:
Possible Questions:
What about the “XYZ” from “ABC” Tools?
Let me take a note of that and talk to our partnership team so they can talk to ABC and see what it would take to have support for their development tools.
What about Arria 10 SoC?:
Unless SW development Tools face challenges because of the change in Altera’s HPS architecture (moving the memory controller outside the HPS and reducing the number of dedicated I/Os to the HPS) in which case the Zynq messages will be even stronger, these messages will remain as powerful.
No Cost
Commercial Offerings
Scalable Offering from Xilinx and Partners to Best Fit your Needs

17. All Programmable Abstractions & AutomationIP
Abstraction
IPI
Automation
Main Messages:
Since the invention of processors, engineers have came up with constant improvements in languages in order to abstract more and more the processor architecture itself (All started with binary language, then came Assembly, then higher level languages such as C, C++, … and then even higher with libraries such as Open GL
From a Hardware standpoint Xilinx is working on duplicating this growing level of abstraction to enhance the level of productivity of the HW designers and there are 2 main tools that are unique to Xilinx for this: A high level Synthesis (Vivado HLS) and an IP-based design flow tool (Vivado IPI)
Note about this slide:
For exact positioning and details on Vivado HLS and Vivado IPI please refer to the presentations from the Tools Product Marketing Team.
The link takes you to some of the details about Vivado and its key value proposition and then continues onto Vivado IPI, Vivado HLS and some intro of Mathworks Simulink and National Instrument Labview
Possible Questions:
What about Arria 10 SoC?:
No change
Next Generation High-level Design Tools

18. OpenCV Library: Accelerating Smarter Vision
Driver
Assist
Broadcast
Monitor HD
Surveillance
Cinema
Projection
Frame-level processing Library for PS
Pixel processing interfaces and basic functions for analytics
Video
Conferencing
Digital
Signage
Vivado HLS
Studio
Cinema Camera
Consumer
Displays
Slide 11: OvenCV
Time on foil: 2 mins
Speaker Notes: Introduction:
Leveraging our All programmable SOC requires solutions that span both the HW and SW domians
To accelerate C/C++ system level design and high-level synthesis (HLS), Xilinx has enhanced its Vivado HLS libraries with support for industry standard floating point math.h operations and real-time video processing functions. Now the over 350 active users and customers evaluating Vivado HLS will have immediate access to video processing functions integrated into an OpenCV environment for embedded vision running on the dual-core ARM processing system. The resulting solution enables up to a 100X performance improvement of existing C/C++ algorithms through hardware acceleration. At the same time, Vivado HLS accelerates system verification and implementation times by up to a 100X compared to RTL design entry flows. When targeting a Zynq All Programmable SoC, design teams can now more rapidly develop C/C++ code for the dual-core ARM processing system, while compute intensive functions are automatically accelerated in the high performance FPGA fabric. 
Office-class
MFP
Machine
Vision
Medical
Displays

19. Robust Partnership Ecosystem
Over 100 Zynq Specific Partners … and Growing
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20. Robust Partnership Ecosystem
ZC702
ZED
ZC706
Wide distribution of Zynq-7000 AP SoC based boards/kits
ZC702 & ZED-Board (Zynq-7020), ZC706 (Zynq-7045)
>4000 boards/kits shipped between Xilinx and Avnet.
Large selection of boards/kits for different end uses and applications
GPOS & RTOS Board Support Packages
Market Specific Kits: ISM Video, Intelligent Vision. Real-Time AVB, Automotive Vision,
and more coming
Over a dozen independent Zynq SOM vendors
Announced over ~½ dozen new SOMs at Embedded World 2013
Over 100 Zynq Specific Partners … and Growing
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21. Comprehensive Operating Systems Offering
More than 95% of commercial embedded operating systems supported on Zynq- 7000
Scalable solution ranging from Real Time Operating Systems to fully featured Operating Systems
Safety critical certifications in key industry segments
Multi-core support in SMP and AMP mode
Robust open source initiative for Linux and Android

22. Best-In-Class Operating SystemsOS
Provider
Version
Availability (ZC702 board support)
Linux
ENEA Linux
ENEA
3.0
Now
WR Linux 5
Wind River
3.4
MVL CGE6
Montavista
2.6.32
LinuxLink
Timesys NA
Android
iVeia
4.2.2
Windows Embedded Compact 7/2013
Adeneo Embedded 7
VxWorks
6.9.3
INTEGRITY
GreenHills Software
QNX
Adeneo Embedded/QNX
6.5
OSE
5.5
ThreadX/NetX
Express Logic
FreeRTOS
Xilinx
7.x
RTA-OS SC1-4
ETAS
Now (single core)
eCOS
ITR
eT-Kernel
eSOL
TBD
µc/OS
Micrium II
Nucleus
Mentor
Quadros

23. Zynq: the Perfect Platform for Smarter Vision
Broadcast Reference Monitor
Machine Vision
Driver Assist
Cinema Projection
HD Surveillance
Digital Signage
Telepresence
Consumer Video Displays
Studio / Cinema
Camera
Time on foil: 2mins
Speaker Notes: Main:
What we have is the Perfect Platform for Smarter Vision and we call it Zynq.
It is the optimal combination of Software Programmability, Hardware Programmability and I/O Programmability all in on silicon device to enable all these applications.
We have everything from Driver’s Assistance and Machine Vision to Broadcast Reference Monitors and Digital Cinema projectors to Medical Displays and A&D UAV’s. In fact we have rolled up almost 30 different applications that Zynq is a good fit. On the website we have highlighted 11 of these design examples for you to use with customers.
So how does it compare to other solutions in the market?
Key Take-a-way:
Objective of slide:
A&D UAV
Office-class MFP
Medical Display

24. Zynq Delivers Video Performance & Flexibility
Simplified Image Processing Signal Chain vs. Requirements
Time on foil: 5mins
Speaker Notes: Main:
Zynq Delivers the best video performance and flexibility. There is nothing else short of full custom ASICs that can match the video pixel processing power of an All Programmable SoC.
What is shown here is a typical image processing chain. A display processing chain is similar as well.
As you see in the grey functional blocks from the camera lens and CMOS sensor you need to bring the image into Zynq via an input interface like MIPI. Once you have received the image, then you can perform various image and video processing on that image. In this case we highlight the compute requirements of 4K2K at around 240Gops. Most embedded GPUs run out of steam at around 60 Gops and DSPs are just not good at pixel processing, period.
From this image and video processing, we then do the Video Analytic Object Segmentation in the Programmable FPGA where you need that unmatched pixel processing power and this takes another Gops of performance and then everything is handed off to the ARM processor to analyze the video analytics and then load this information as well as much more into a Metadata information container. On top of this since you have dual cores, the system is also doing the system management and control and communication functions as well.
At this time you are now preparing to output the video and then you may need to do graphics overlay and then some encoding of the video image with H.264 or H.265/HEVC to bring the data stream or file to a manageable size which will require another Gops of performance.
Then finally you need to be able to output the video across multiple video interfaces such as SDI, HDMI, DisplayPort or even IP technology like EthernetAVB.
As you can see, Zynq is the only device that can enable this whole system solution, the DSP and GPU solutions have to make compromised decisions to put in Fixed IP tied to Fixed IO to be able to come up with something that still does not match the performance of Zynq.
Let’s take a quick peak at one example.
Key Take-a-way:
Objective of slide:

25. HW Acceleration with Zynq PL
Zynq customer’s can “unload” DSP functionality onto the PL. 
A“rule of thumb” is ~20% of C code consumes 80% of a processor’s bandwidth
When engineers run out of processor bandwidth, they can profile their code, isolate the most clock consuming functions and port it into the Zynq PL
Xilinx FPGA based DSP has extensive performance and overclocking capabilities
Time on foil: 5mins
Speaker Notes: Main:
Zynq Delivers the best video performance and flexibility. There is nothing else short of full custom ASICs that can match the video pixel processing power of an All Programmable SoC.
What is shown here is a typical image processing chain. A display processing chain is similar as well.
As you see in the grey functional blocks from the camera lens and CMOS sensor you need to bring the image into Zynq via an input interface like MIPI. Once you have received the image, then you can perform various image and video processing on that image. In this case we highlight the compute requirements of 4K2K at around 240Gops. Most embedded GPUs run out of steam at around 60 Gops and DSPs are just not good at pixel processing, period.
From this image and video processing, we then do the Video Analytic Object Segmentation in the Programmable FPGA where you need that unmatched pixel processing power and this takes another Gops of performance and then everything is handed off to the ARM processor to analyze the video analytics and then load this information as well as much more into a Metadata information container. On top of this since you have dual cores, the system is also doing the system management and control and communication functions as well.
At this time you are now preparing to output the video and then you may need to do graphics overlay and then some encoding of the video image with H.264 or H.265/HEVC to bring the data stream or file to a manageable size which will require another Gops of performance.
Then finally you need to be able to output the video across multiple video interfaces such as SDI, HDMI, DisplayPort or even IP technology like EthernetAVB.
As you can see, Zynq is the only device that can enable this whole system solution, the DSP and GPU solutions have to make compromised decisions to put in Fixed IP tied to Fixed IO to be able to come up with something that still does not match the performance of Zynq.
Let’s take a quick peak at one example.
Key Take-a-way:
Objective of slide:

26. Smarter Solutions than ASICs and ASSPs Surveillance
System
Performance
BOM
Cost
Total
Power
Programmable Systems Integration
2-4 Chips  1 Chip
Accelerated Design Productivity
- 16%
- 30%
+2x
Needs Marcom clean up
Traditional FPGA
Xilinx SmartCORE
Zynq-7000
ASIC/ASSP

27. Smarter Solutions than ASICs and ASSPs Monitors and Projection
System
Performance
BOM
Cost
Total
Power
Programmable Systems Integration
3 Chips  1 Chip
Accelerated Design Productivity
- 40%
- 50%
+2x
Needs Marcom clean up
Traditional FPGA
Xilinx SmartCORE
Zynq-7000
ASIC/ASSP

28. Smarter Solutions than ASICs and ASSPs Driver Assistance
System
Performance
BOM
Cost
Total
Power
Programmable Systems Integration
3 Chips  1 Chip
Accelerated Design Productivity
- 25%
- 50%
+2x
Needs Marcom clean up
Traditional FPGA
Xilinx SmartCORE
Zynq-7000
ASIC/ASSP

29. Smarter Solutions than ASICs and ASSPs Broadcast Camera
System
Performance
BOM
Cost
Total
Power
Programmable Systems Integration
9 Chips  3 Chip
Accelerated Design Productivity
- 30%
- 60%
+2x
Needs Marcom clean up
Traditional FPGA
Xilinx SmartCORE
Zynq-7000
ASIC/ASSP

30. Summary Zynq-7000 Integration Power Performance BOM Cost Productivity
Enabling Smarter Vision
Most efficient ARM + FPGA for analytics & control
Most extensive OS, middleware & stack ecosystem
Highest level of security & reliability
Unmatched Performance and Power
Optimized PS/PL interconnect with HW acceleration
Best Price/Performance/Watt
Strongest Heterogeneous Processing Roadmap
Proven Productivity
Industry leading High Level Synthesis
Widest selection of SW environments & tools
Largest portfolio of IP, design kits & reference designs
Main Messages:
Zynq is a generation ahead of any competing solution as it is the smartest solution for customers to use
The reasons for this or “proof points” have been classified in 3 categories
Enabling Smartest Systems which represents what were some of the key decisions that we made early on (beyond just pushing performance and power) to enable customers to leverage a truly unique product offering
Unmatched Performance and Power highlights the 3 main areas that were important for us to get right (and we did) in order to offer the best performance at the lowest power compared to competing solutions such as SoC FPGA
Proven Productivity is also here because this is becoming a growing concern for customers, and it important to show that we have taken many steps to facilitate the development and deployment of Zynq based systems, as much on the SW side than the HW side with Tools such as Vivado HLS
Those 3 categories and 9 tenets show the key value that zynq offers and why we have been stating that Zynq is a generation ahead of any competing solution out there.
Note about this slide:
The 9 tenets all have strong messages against Altera but also represent a good classification of the values that Zynq and Xilinx bring to the Embedded space. Even outside of a Gen Ahead discussion, they are worth using as the baseline as they represent solid foundations to the value of Zynq
What about Arria X SoC?:
As you can see, the messages have changed a bit from the time where Altera had not announced Arria 10 SoC. Only changed a bit because the announcement of Arria 10 SoC does not really change the playing field given that it is a complete paper product and for us to give much credibility to Altera on their Arria 10 SoC, they would need first to execute on their Arria V SoC.
That being said, although Arria 10 SoC is a paper product, it may still resonate with customers who are willing to take Altera at face value and for this, the 9 tenets have changed a bit.
The first 3 tenets have not changed because Altera has not changed their HPS to FPGA interface, they still have to catch up with our OS offering and their improvements in security are still short of Zynq
The power and performance is the one that changed the most because Altera is now claiming 1.5GHz, but until they deliver Zynq will remain the first and UNIQUE SoC of its class with 1GHz performance. The 20nm process should also put Arria 10 SoC on par (or close) to Zynq-7000 in terms of FPGA performance and most likely at a slight advantage on power, but this will come with the hefty cost of 20nm, so Arria 10 SoC is likely to be a no go for most customers from a cost standpoint and therefore Zynq will offer in most cases the best Price/Performance per Watt.
Altera also lacked to understand that customers are looking for integration and processor frequency is only one element. The Next Gen Zynq will offer significant advantage for most customers requiring more than just pure MHz increase from the processors by leading the way in heterogeneous processing. More details on this in the specific section
Lastly our advantage in productivity remains unchanged as the HW and SW design tools that we offer (and that Support Zynq) are far beyond what Altera has and will have in the coming months at least.
One thing to keep in mind is that Altera’s choice to go with a DDR memory controller into the FPGA (and not in the HPS anymore) will likely bring SW portability challenges highlighting even more Xilinx’s leadership.