1. Computer Architecture and Parallel Computing 并行结构与计算 Lecture 3 - Memory Peng LIU ( 刘鹏 ) College of Information Science & Electronic Engineering Zhejiang University 浙江大学信息与电子工程学院 liupeng@zju.edu.cn May 25, 2015

2. Early Read-Only Memory Technologies 2 Punched cards, From early 1700s through Jaquard Loom, Babbage, and then IBM Punched paper tape, instruction stream in Harvard Mk 1 IBM Card Capacitor ROS IBM Balanced Capacitor ROS Diode Matrix, EDSAC-2 µcode store

3. Early Read/Write Main Memory Technologies 3 Williams Tube, Manchester Mark 1, 1947 Babbage, 1800s: Digits stored on mechanical wheels Mercury Delay Line, Univac 1, 1951 Also, regenerative capacitor memory on Atanasoff-Berry computer, and rotating magnetic drum memory on IBM 650

4. 4 Core Memory Core memory was first large scale reliable main memory –invented by Forrester in late 40s/early 50s at MIT for Whirlwind project Bits stored as magnetization polarity on small ferrite cores threaded onto two-dimensional grid of wires Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads) DEC PDP-8/E Board, 4K words x 12 bits, (1968) Robust, non-volatile storage Used on space shuttle computers until recently Cores threaded onto wires by hand (25 billion a year at peak production) Core access time ~ 1  s

5. 5 Semiconductor Memory Semiconductor memory began to be competitive in early 1970s –Intel formed to exploit market for semiconductor memory –Early semiconductor memory was Static RAM (SRAM). SRAM cell internals similar to a latch (cross-coupled inverters). First commercial Dynamic RAM (DRAM) was Intel 1103 –1Kbit of storage on single chip –charge on a capacitor used to hold value Semiconductor memory quickly replaced core in ‘70s

6. 6 One Transistor Dynamic RAM [Dennard, IBM] TiN top electrode (V REF ) Ta 2 O 5 dielectric W bottom electrode poly word line access transistor 1-T DRAM Cell word bit access transistor Storage capacitor (FET gate, trench, stack) V REF

7. Modern DRAM Structure 7 [Samsung, sub-70nm DRAM, 2004]

8. 8 DRAM Architecture Row Address Decoder Col. 1 Col. 2 M Row 1 Row 2 N Column Decoder & Sense Amplifiers M N N+M bit lines word lines Memory cell (one bit) D Data Bits stored in 2-dimensional arrays on chip Modern chips have around 4-8 logical banks on each chip – each logical bank physically implemented as many smaller arrays

9. 9 DRAM Packaging (Laptops/Desktops/Servers) DIMM (Dual Inline Memory Module) contains multiple chips with clock/control/address signals connected in parallel (sometimes need buffers to drive signals to all chips) Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts) Address lines multiplexed row/column address Clock and control signals Data bus (4b,8b,16b,32b) DRAM chip ~12 ~7

10. DRAM Packaging, Mobile Devices 10 [ Apple A4 package cross-section, iFixit 2010 ] Two stacked DRAM die Processor plus logic die [ Apple A4 package on circuit board]

11. 11 DRAM Operation Three steps in read/write access to a given bank Row access (RAS) –decode row address, enable addressed row (often multiple Kb in row) –bitlines share charge with storage cell –small change in voltage detected by sense amplifiers which latch whole row of bits –sense amplifiers drive bitlines full rail to recharge storage cells Column access (CAS) –decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package) –on read, send latched bits out to chip pins –on write, change sense amplifier latches which then charge storage cells to required value –can perform multiple column accesses on same row without another row access (burst mode) Precharge –charges bit lines to known value, required before next row access Each step has a latency of around 15-20ns in modern DRAMs Various DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architecture

12. 12 Double-Data Rate (DDR2) DRAM [ Micron, 256Mb DDR2 SDRAM datasheet ] RowColumnPrechargeRow’ Data 200MHz Clock 400Mb/s Data Rate

13. 13 CPU-Memory Bottleneck Memory CPU Performance of high-speed computers is usually limited by memory bandwidth & latency Latency (time for a single access) Memory access time >> Processor cycle time Bandwidth (number of accesses per unit time) if fraction m of instructions access memory, 1+m memory references / instruction CPI = 1 requires 1+m memory refs / cycle (assuming MIPS RISC ISA)

14. Processor-DRAM Gap (latency) 14 Four-issue 3GHz superscalar accessing 100ns DRAM could execute 1,200 instructions during time for one memory access!

15. Physical Size Affects Latency 15 Small Memory CPU Big Memory CPU Signals have further to travel Fan out to more locations

16. 16 Relative Memory Cell Sizes [ Foss, “Implementing Application-Specific Memory”, ISSCC 1996 ] DRAM on memory chip On-Chip SRAM in logic chip

17. 17 Memory Hierarchy Small, Fast Memory (RF, SRAM) capacity: Register << SRAM << DRAM latency: Register << SRAM << DRAM bandwidth: on-chip >> off-chip On a data access: if data  fast memory  low latency access (SRAM) if data  fast memory  long latency access (DRAM) CPU Big, Slow Memory (DRAM) AB holds frequently used data

18. 18 Management of Memory Hierarchy Small/fast storage, e.g., registers –Address usually specified in instruction –Generally implemented directly as a register file »but hardware might do things behind software’s back, e.g., stack management, register renaming Larger/slower storage, e.g., main memory –Address usually computed from values in register –Generally implemented as a hardware-managed cache hierarchy »hardware decides what is kept in fast memory »but software may provide “hints”, e.g., don’t cache or prefetch

19. Real Memory Reference Patterns Donald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): 168-192 (1971) Time Memory Address (one dot per access)

20. Typical Memory Reference Patterns Address Time Instruction fetches Stack accesses Data accesses n loop iterations subroutine call subroutine return argument access vector access scalar accesses

21. Common Predictable Patterns Two predictable properties of memory references: –Temporal Locality: If a location is referenced it is likely to be referenced again in the near future. –Spatial Locality: If a location is referenced it is likely that locations near it will be referenced in the near future.

22. Memory Reference Patterns Donald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): 168-192 (1971) Time Memory Address (one dot per access) Spatial Locality Spatial Locality Temporal Locality Temporal Locality

23. Caches Caches exploit both types of predictability: –Exploit temporal locality by remembering the contents of recently accessed locations. –Exploit spatial locality by fetching blocks of data around recently accessed locations.

24. Inside a Cache CACHE Processor Main Memory Address Data Address Tag Data Block Data Byte Data Byte Data Byte Line 100 304 6848 copy of main memory location 100 copy of main memory location 101 416

25. Cache Algorithm (Read) Look at Processor Address, search cache tags to find match. Then either Found in cache a.k.a. HIT Return copy of data from cache Not in cache a.k.a. MISS Read block of data from Main Memory Wait … Return data to processor and update cache Q: Which line do we replace?

26. 26 Placement Policy 0 1 2 3 4 5 6 7 0 1 2 3 Set Number Cache Fully (2-way) Set Direct AssociativeAssociative Mapped anywhereanywhere in only into set 0 block 4 (12 mod 4) (12 mod 8) 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 2 2 2 2 2 2 2 2 2 2 0 1 2 3 4 5 6 7 8 9 3 0 1 Memory Block Number block 12 can be placed

27. Direct-Mapped Cache TagData Block V = Block Offset TagIndex t k b t HIT Data Word or Byte 2 k lines

28. Direct Map Address Selection higher-order vs. lower-order address bits TagData Block V = Block Offset Index t k b t HIT Data Word or Byte 2 k lines Tag

29. 2-Way Set-Associative Cache

30. Fully Associative Cache

31. 31 Replacement Policy In an associative cache, which block from a set should be evicted when the set becomes full? Random Least-Recently Used (LRU) LRU cache state must be updated on every access true implementation only feasible for small sets (2-way) pseudo-LRU binary tree often used for 4-8 way First-In, First-Out (FIFO) a.k.a. Round-Robin used in highly associative caches Not-Most-Recently Used (NMRU) FIFO with exception for most-recently used block or blocks This is a second-order effect. Why? Replacement only happens on misses

32. 32 Word3Word0Word1Word2 Block Size and Spatial Locality Larger block size has distinct hardware advantages less tag overhead exploit fast burst transfers from DRAM exploit fast burst transfers over wide busses What are the disadvantages of increasing block size? block address offset b 2 b = block size a.k.a line size (in bytes) Split CPU address b bits 32-b bits Tag Block is unit of transfer between the cache and memory 4 word block, b=2 Fewer blocks => more conflicts. Can waste bandwidth.

33. 33 CPU-Cache Interaction (5-stage pipeline) PC addr inst Primary Instruction Cache 0x4 Add IR D nop hit ? PCen Decode, Register Fetch wdata R addr wdata rdata Primary Data Cache we A B YY ALU MD1 MD2 Cache Refill Data from Lower Levels of Memory Hierarchy hit ? Stall entire CPU on data cache miss To Memory Control M E

34. 34 Improving Cache Performance Average memory access time = Hit time + Miss rate x Miss penalty To improve performance: reduce the hit time reduce the miss rate reduce the miss penalty What is the simplest design strategy? Biggest cache that doesn’t increase hit time past 1-2 cycles (approx 8-32KB in modern technology) [ design issues more complex with out-of-order superscalar processors ]

35. Serial-versus-Parallel Cache and Memory access  is HIT RATIO: Fraction of references in cache 1 -  is MISS RATIO: Remaining references CACHE Processor Main Memory Addr Data Average access time for serial search: t cache + (1 - ) t mem CACHE Processor Main Memory Addr Data Average access time for parallel search:  t cache + (1 - ) t mem Savings are usually small, t mem >> t cache, hit ratio  high High bandwidth required for memory path Complexity of handling parallel paths can slow t cache

36. 36 Causes for Cache Misses Compulsory: first-reference to a block a.k.a. cold start misses - misses that would occur even with infinite cache Capacity: cache is too small to hold all data needed by the program - misses that would occur even under perfect replacement policy Conflict: misses that occur because of collisions due to block-placement strategy - misses that would not occur with full associativity

37. 37 Effect of Cache Parameters on Performance Larger cache size + reduces capacity and conflict misses - hit time will increase Higher associativity + reduces conflict misses - may increase hit time Larger block size + reduces compulsory and capacity (reload) misses - increases conflict misses and miss penalty

38. 38 Write Policy Choices Cache hit: –write through: write both cache & memory »Generally higher traffic but simpler pipeline & cache design –write back: write cache only, memory is written only when the entry is evicted »A dirty bit per block further reduces write-back traffic »Must handle 0, 1, or 2 accesses to memory for each load/store Cache miss: –no write allocate: only write to main memory –write allocate (aka fetch on write): fetch into cache Common combinations: –write through and no write allocate –write back with write allocate

39. 39 Write Performance Tag Data V = Block Offset TagIndex t k b t HIT Data Word or Byte 2 k lines WE

40. 40 Reducing Write Hit Time Problem: Writes take two cycles in memory stage, one cycle for tag check plus one cycle for data write if hit Solutions: Design data RAM that can perform read and write in one cycle, restore old value after tag miss Fully-associative (CAM Tag) caches: Word line only enabled if hit Pipelined writes: Hold write data for store in single buffer ahead of cache, write cache data during next store’s tag check

41. 41 Pipelining Cache Writes TagsData TagIndexStore Data Address and Store Data From CPU Delayed Write DataDelayed Write Addr. =? Load Data to CPU Load/Store L S 10 Hit? Data from a store hit written into data portion of cache during tag access of subsequent store

42. 42 Write Buffer to Reduce Read Miss Penalty Processor is not stalled on writes, and read misses can go ahead of write to main memory Problem: Write buffer may hold updated value of location needed by a read miss Simple scheme: on a read miss, wait for the write buffer to go empty Faster scheme: Check write buffer addresses against read miss addresses, if no match, allow read miss to go ahead of writes, else, return value in write buffer Data Cache Unified L2 Cache RF CPU Write buffer Evicted dirty lines for writeback cache OR All writes in writethrough cache

43. 43 Block-level Optimizations Tags are too large, i.e., too much overhead –Simple solution: Larger blocks, but miss penalty could be large. Sub-block placement (aka sector cache) –A valid bit added to units smaller than full block, called sub-blocks –Only read a sub-block on a miss –If a tag matches, is the word in the cache? 100 300 204 1 1 1 1 0 0 0 1

44. 44 Multilevel Caches Problem: A memory cannot be large and fast Solution: Increasing sizes of cache at each level CPU L1$ L2$ DRAM Local miss rate = misses in cache / accesses to cache Global miss rate = misses in cache / CPU memory accesses Misses per instruction = misses in cache / number of instructions

45. 45 Presence of L2 influences L1 design Use smaller L1 if there is also L2 –Trade increased L1 miss rate for reduced L1 hit time and reduced L1 miss penalty –Reduces average access energy Use simpler write-through L1 with on-chip L2 –Write-back L2 cache absorbs write traffic, doesn’t go off-chip –At most one L1 miss request per L1 access (no dirty victim write back) simplifies pipeline control –Simplifies coherence issues –Simplifies error recovery in L1 (can use just parity bits in L1 and reload from L2 when parity error detected on L1 read)

46. 46 Inclusion Policy Inclusive multilevel cache: –Inner cache holds copies of data in outer cache –External coherence snoop access need only check outer cache Exclusive multilevel caches: –Inner cache may hold data not in outer cache –Swap lines between inner/outer caches on miss –Used in AMD Athlon with 64KB primary and 256KB secondary cache Why choose one type or the other?

47. 47 Itanium-2 On-Chip Caches (Intel/HP, 2002) Level 1: 16KB, 4-way s.a., 64B line, quad-port (2 load+2 store), single cycle latency Level 2: 256KB, 4-way s.a, 128B line, quad-port (4 load or 4 store), five cycle latency Level 3: 3MB, 12-way s.a., 128B line, single 32B port, twelve cycle latency

48. Power 7 On-Chip Caches [IBM 2009] 48 32KB L1 I$/core 32KB L1 D$/core 3-cycle latency 256KB Unified L2$/core 8-cycle latency 32MB Unified Shared L3$ Embedded DRAM 25-cycle latency to local slice

49. 49 Prefetching Speculate on future instruction and data accesses and fetch them into cache(s) –Instruction accesses easier to predict than data accesses Varieties of prefetching –Hardware prefetching –Software prefetching –Mixed schemes What types of misses does prefetching affect?

50. 50 Issues in Prefetching Usefulness – should produce hits Timeliness – not late and not too early Cache and bandwidth pollution L1 Data L1 Instruction Unified L2 Cache RF CPU Prefetched data

51. 51 Hardware Instruction Prefetching Instruction prefetch in Alpha AXP 21064 –Fetch two blocks on a miss; the requested block (i) and the next consecutive block (i+1) –Requested block placed in cache, and next block in instruction stream buffer –If miss in cache but hit in stream buffer, move stream buffer block into cache and prefetch next block (i+2) L1 Instruction Unified L2 Cache RF CPU Stream Buffer Prefetched instruction block Req block Req block

52. 52 Hardware Data Prefetching Prefetch-on-miss: –Prefetch b + 1 upon miss on b One Block Lookahead (OBL) scheme –Initiate prefetch for block b + 1 when block b is accessed –Why is this different from doubling block size? –Can extend to N-block lookahead Strided prefetch –If observe sequence of accesses to block b, b+N, b+2N, then prefetch b+3N etc. Example: IBM Power 5 [2003] supports eight independent streams of strided prefetch per processor, prefetching 12 lines ahead of current access

53. 53 Software Prefetching for(i=0; i < N; i++) { prefetch( &a[i + 1] ); prefetch( &b[i + 1] ); SUM = SUM + a[i] * b[i]; }

54. 54 Software Prefetching Issues Timing is the biggest issue, not predictability –If you prefetch very close to when the data is required, you might be too late –Prefetch too early, cause pollution –Estimate how long it will take for the data to come into L1, so we can set P appropriately – Why is this hard to do? for(i=0; i < N; i++) { prefetch( &a[i + P ] ); prefetch( &b[i + P ] ); SUM = SUM + a[i] * b[i]; } Must consider cost of prefetch instructions

55. 55 Compiler Optimizations Restructuring code affects the data block access sequence –Group data accesses together to improve spatial locality –Re-order data accesses to improve temporal locality Prevent data from entering the cache –Useful for variables that will only be accessed once before being replaced –Needs mechanism for software to tell hardware not to cache data (“no-allocate” instruction hints or page table bits) Kill data that will never be used again –Streaming data exploits spatial locality but not temporal locality –Replace into dead cache locations

56. 56 Loop Interchange for(j=0; j < N; j++) { for(i=0; i < M; i++) { x[i][j] = 2 * x[i][j]; } } for(i=0; i < M; i++) { for(j=0; j < N; j++) { x[i][j] = 2 * x[i][j]; } } What type of locality does this improve?

57. 57 Loop Fusion for(i=0; i < N; i++) a[i] = b[i] * c[i]; for(i=0; i < N; i++) d[i] = a[i] * c[i]; for(i=0; i < N; i++) { a[i] = b[i] * c[i]; d[i] = a[i] * c[i]; } What type of locality does this improve?

58. 58 for(i=0; i < N; i++) for(j=0; j < N; j++) { r = 0; for(k=0; k < N; k++) r = r + y[i][k] * z[k][j]; x[i][j] = r; } Matrix Multiply, Naïve Code Not touchedOld accessNew access xj i yk i zj k

59. 59 for(jj=0; jj < N; jj=jj+B) for(kk=0; kk < N; kk=kk+B) for(i=0; i < N; i++) for(j=jj; j < min(jj+B,N); j++) { r = 0; for(k=kk; k < min(kk+B,N); k++) r = r + y[i][k] * z[k][j]; x[i][j] = x[i][j] + r; } Matrix Multiply with Cache Tiling What type of locality does this improve? yk i zj k xj i

60. 60 Acknowledgements UCB material derived from course CS152 Harvard University material derived from course CS246 MIT material derived from course 6.888 Parallel and Heterogeneous Computer Architecture

61. Readings Is Dark Silicon Useful?, Taylor, DAC12 Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?, Chung et al., MICRO10 Dark Silicon and the End of Multicore Scaling, Esmaeilzadeh et al., ISCA11 Additional: Amdahl's Law in the multicore era, Advancing systems without technology progressIs Dark Silicon Useful? Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? Dark Silicon and the End of Multicore ScalingAmdahl's Law in the multicore era Advancing systems without technology progress

62. Evaluating parallel systems: Principles, tools, and experiment design Memory system characterization of commercial workloads, Barroso et al., ISCA98 Memory system characterization of commercial workloads Emulation track: RAMP BlueRAMP Blue FPGA-accelerated simulation track: HASimHASim Software simulation track: gem5gem5 Additional: A Characterization of Processor Performance in the VAX-11/780, IPC Considered Harmful for Multiprocessor Workloads, CACTI;A Characterization of Processor Performance in the VAX-11/780IPC Considered Harmful for Multiprocessor WorkloadsCACTI Emulation: ProtoFlex, Leon; FPGA-accelerated: FAST, RAMP Gold;ProtoFlexLeonFASTRAMP Gold Software sim: ASim, Graphite, WWTASimGraphiteWWT 62