1. 1 강의노트 10 Design of Sequential Logics using State Machine Design technique based on Advanced Digital Logic Design, Chapter 5, by Sunggu Lee, Thomson publishing, 2006

2. 2 Contents Manual state machine design  How to design state machines for complex synchronous sequential digital logic circuits “Automatic” state machine design  How to convert algorithmic descriptions into HDL code that can be synthesized into working circuits  The general form of the circuit that will be synthesized from an algorithmic HDL description

3. 3 State Machine Design Used for systematic design of synchronous sequential digital logic circuits Modification of FSM Method  FSM (Finite State Machine) method insufficient  FSM method only suitable for small sequential circuits with small numbers of external inputs Allow more complicated checks for state transitions Uses RTL statements within the states  Within one state, all RTL statements execute concurrently Permits systematic conversion from algorithms to H/W

4. 4 Manual State Machine Design Method (1) Pseudocode  create an algorithm to describe desired circuit operation (2) RTL Program  convert the pseudocode into an RTL Program (HDL or ASM chart format) (3) Datapath  design the datapath based on the RTL Program (4) State Machine (State Diagram)  based on the RTL Program and the signals defined in the datapath (5) Control Logic Design  based on the state diagram

5. 5 (1) Algorithms Formal definition of an “algorithm”  A general step-by-step procedure for solving a problem that is CORRECT and TERMINATES. Properties of an algorithm  Well-ordered: There is a clear order in which to do the operations.  Unambiguous: Each operation is clearly understood by all intended computing agents.  Effectively computable: The computing agent has ability to carry out each operation.  Finite time: Each operation takes finite time and there will be a finite number of steps. Informal definition of an “algorithm”  A computer-program-like procedure for solving the problem given. Algorithm description methods  Old (outdated) method: flowchart  Pseudocode: free-form procedural description

6. 6 (2) RTL Program HDL Format  Like a pseudocode description, except that each “step” is one state of the state machine All operations within one state execute concurrently  All operations are RTL operations ASM Chart Format  Uses a graphical notation that resembles a flowchart  Main difference All operations within one state execute concurrently

7. 7 Structure of General Synchronous Sequential Circuit

8. 8 Partitioning of Digital Circuits (3) Datapath Section  all logic not included in the control logic section registers, adders, counters, multiplexers, etc.  typically the “word”-sized data manipulation and storage components through which the data “flows” (5) Control Logic Section  logic required to generate control signals for registers, adders, counters, etc.  “State registers and state transition logics”

9. 9 (4) State Machine - example Similar to FSM  in state transition represent  in Moore type output represent Similar to ASM  in RTL statements use in a state Naturally the output only depends on the state. Most widely used in the industry

10. 10 General template for synchronous sequential circuits

11. 11 Example1: Factorial Circuits Pseudocode Step1. fact(15:0)  1; done  0; Step 2. For i=2 to n do fact  fact * i; Step 3. done  1;

12. 12 Example1: Factorial Circuits RTL Program Step1. fact(15:0)  1; done  0; count  2; Step 2. if (count ≤ n) then begin fact  fact * count; count  count + 1; go to Step 2; end Step 3. done  1;

13. 13 Example1: Factorial Circuits RTL Program Step1. fact(15:0)  1; done  0; count  2; Step 2. if (count ≤ n) then begin count  count + 1; fact  fact * count; go to Step 2; end Step 3. done  1; Each “step” corresponds to a “state” in the control logic. The RTL operations within a single “state” are executed concurrently.

14. 14 Datapath design rule of thumb 1.Every unique variable that is assigned a value in the RTL program can be implemented as a register (PIPO, Shift register, counter, etc.). 2.If there is a variable that is assigned different values at different points in the RTL program, then a multiplexer or a tri-state bus structure is necessary. 3.Accepts Control signal inputs to control the operation of the various datapath components. 4.Produce Status signal outputs to Control logic. 5.A few optimizations may be possible by combining registers, adders or other components. Detailed datapath design will be touched in the next semester.

15. 15 Rule of thumb applied in our example 1.Every unique variable that is assigned a value in the RTL program can be implemented as a register (PIPO, Shift register, counter, etc.) count, fact in our example fact can be implemented with a simple register; count with a counter 2.If there is a variable that is assigned different values at different points in the RTL program, then a multiplexer or a tri- state bus structure is necessary. fact is either initialized or have the value fact*count 3.Accepts Control signal inputs to control the operation of the various datapath components. 4.Produce Status signal outputs to Control logic. 5.A few optimizations may be possible by combining registers, adders or other components.

16. 16 Example1: Factorial Circuits - Datapath Control Signals Status Signals

17. 17 Control Logic Design Methods One-FF-per-state method  also referred to as “one-hot encoded” or “delay element” method  uses one FF for each state of the state machine Binary encoded state method  uses encoded states number of FFs used = integer_part (log (number_of_states))  results in the most compact implementation Gray encoded state method Sequence-counter method  for use with cyclical state transition patterns e.g., a CPU with equal numbers of states for each instruction  outputs of the “counter” are the control logic “states”

18. 18 One-FF-Per-State Method Uses one-to-one transformations from state diagram to digital logic components  Also applicable to ASM charts Transformations  state in state diagram transforms to a D flip-flop  transition from one state to another in state diagram transforms to a path from the Q or Q’ output of one state flip-flop to the D input another D flip-flop  labeled transition in state diagram AND gate with the labeled condition labeled (conditional) signal activation also leads to AND gate  Several transitions into a single state OR gate with one input for each transition

19. 19 One-FF-Per-State Method Example

20. 20 Conversion from ASM chart to logic

21. 21 Example1: Factorial Circuits – State diagram For the Control logic design, a state diagram is helpful. The state diagram here is restrictive diagram than formal Finite State Machine (FSM). Status Signals Control Signals

22. 22 Example1: Factorial Circuits – Control logic

23. 23 Example1: Factorial Circuits – Control logic

24. 24 Example2: Four-Phase Handshake Transmitter Circuit Used to communicate between two circuits in different clock domains (i.e., clocked by different clock signals)  In large or high-performance circuits, different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits.  Communication of data packets between such circuits requires a handshaking protocol

25. 25 Handshake protocols ACK: indicates successful data receipt. Indicates ready-to-receive.

26. 26 Example2: Four-Phase Handshake Transmitter Circuit: Pseudocode 1. req  0; wait until ready = 1; -- data ready 2. DATA  data_to_be_sent; 3. req  1; -- assert request wait until ack = 1; 4. req  0; wait until ack = 0; 5. go to Step 1;

27. 27 Example2: Four-Phase Handshake Transmitter Circuit: ASM Chart

28. 28 Example 2: Overall block diagram req is output. data_to_be_sent, ready and ack are inputs. Ack Data_to_be_sent Ready Data Req

29. 29 Example2: ASM Chart to Datapath There is only one variable in the pseudocode: DATA

30. 30 Example2: Four-Phase Handshake Transmitter Circuit: ASM Chart to Logic

31. 31 Overall Manual State Machine Design Approach Write down a pseudocode solution  test it out using a short computer program Convert the pseudocode to an RTL program  try to “optimize” ASM chart, so it uses a small number of states  can use HDL format or ASM chart format Derive the datapath from the RTL program  figure out the datapath components and signals needed Form a state diagram with states and control signal activations Derive the control logic design  one-hot or PLD-based approach

32. 32 Contents Manual state machine design  How to design state machines for complex synchronous sequential digital logic circuits “Automatic” state machine design  How to convert algorithmic descriptions into HDL code that can be synthesized into working circuits  The general form of the circuit that will be synthesized from an algorithmic HDL description

33. 33 Automatic State Machine Design 1.Describe the desired circuit using pseudocode.  Many engineers adopt C itself as the language for pseudocode in order to simulate and to verify the algorithm. 2.Convert the pseudocode into an HDL program.  Conversion from an ASM chart into a synthesizable VHDL code can be done through special EDA tools.  Inherently concurrent nature of hardware must be kept in mind when writing an HDL code. 3.Use a synthesis tool to convert the HDL code into a working hardware circuit.  Implement for the target hardware architecture.

34. 34 Recommended Pseudocode Format for HDL code conversion (0) initialize variables; while (true) do (1) first step of algorithm; (2) second step of algorithm;... (k) for (i = 0; i < max; i++) …... (m) call to function FUNCTION; … (n) n’th step of algorithm endwhile

35. 35 Recommended Pseudocode Format for HDL code conversion Initialization is followed by an infinite while loop. Operation in while loop can include  assignment to variables  arithmetic/logic operations  conditional actions  calls to subroutines/functions  for/while loops. Loops can be either with operations that can be performed  concurrently  or as a series of sequential steps with delay between the steps.

36. 36 Pseudocode to HDL conversion

37. 37 Corresponding Synthesizable VHDL Code alg: process (reset_n, clk) is begin if (reset_n = ‘0’) then state ‘0’); (other initialization operations); elsif rising_edge(clk) then state -- first step of algorithm when “0001” => … -- second step of algorithm when “0010” => ret_state … when FUNCTION_1 => … -- 1 st step of function … when FUNCTION_1+k => state report “Unknown state!”; end case; end if; -- of elsif rising_edge(clk) end process alg;

38. 38 Example: Two-Phase Handshake Transmitter Circuit Used to communicate between two circuits in different clock domains (i.e., clocked by different clock signals)  In large or high-performance circuits, different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits  Communication of data packets between such circuits requires a handshaking protocol Solution implemented using the automatic synthesis- based method instead of the manual state machine design method used in the previous example.

39. 39 Pseudocode 1. req  0; while (TRUE) do 2. wait until (ready = 1); -- data ready 3. data  data_to_be_sent; 4. req  not req; -- invert req value 5. wait until (ack = req); end while;

40. 40 Synthesizable VHDL Code proc1: process (reset_n, clk) is begin if (reset_n = ‘0’) then req if (ready = ‘0’) then state data req if (ack /= req) then -- case “11” state <= “10”; -- stay in this state until (ack = req) end if; end case; end if; -- of elsif rising_edge(clk) end process proc1;

41. 41 강의노트 11 VHDL module for Memory & Bus

42. 42 Example Memory Components: Volatile:  Random Access Memory (RAM): DRAM "dynamic" SRAM "static" Non-volatile:  Read Only Memory (ROM): Mask ROM "mask programmable" EPROM “ erasable programmable" EEPROM " electrically erasable programmable" FLASH memory - similar to EEPROM with programmer integrated on chip

43. 43 RAM Internals Functionally a RAM is equivalent to a 2-D array of flip-flops (or a set of registers): Cell with write logic: How do we “SEL” a specific register?

44. 44 Standard Internal Memory Organization RAM/ROM naming convention:  examples: 32 X 8, "32 by 8" => 32 8-bit words  1M X 1, "1 meg by 1" => 1M 1-bit words

45. 45 Cascading Memory Modules (or chips) example 256 X 8 memory using 256 X 4 parts: example: 1K X 4 memory using 256 X 4 parts: each module has tri-state outputs:

46. 46 Block diagram for SRAM Asserted ( 인가된다 ): 어떤 신호가 active 상태가 되는 것을 의미. Active-low 신호는 값이 low 일 때 인가되고, active-high 신호는 값 이 high 일 때 인가됨. CS: Chip select. 인가되면 Memory 의 읽고 쓰기가 활성화 됨 OE: Output Enable: 인가되면 memory 의 출력을 외부버스에 실어 줌 WE: Write Enable Functional Equivalent Circuit

47. 47 Read Cycle Timing (a) Address controlled mode: Address 가 변화함으로써 새로운 data 값을 읽는 과정 (b) CS controlled mode: address 는 변화없이, CS 가 인가됨으로써 새로운 data 값을 읽는 과정 t AA 이후 안정된 data 가 출력됨 Address 는 t RC 동안 안정되어 있어야 함 Value change Unstable transition period High impedance, Z

48. 48 CMOS RAM Timing Specifications

49. 49 WE-controlled Write Cycle Timing Period during the signal can change value The signal can have values 0, 1, or Z during this unstable transition period. 이 구간 동안 충돌을 피 하기 위해 Z, 혹은 Din 과 같은 값을 가진다.

50. 50 CS-controlled Write Cycle Timing

51. 51 A simple Memory Model, without considerations for timing spec Integer 로 변환필요, BIT_PACK 에서 정의된 function Address 와 We_b 가 동시에 변하면 이전의 address 값 이 사용되어야 한다. Address’delayed 는 Address 를 델타 delay 만큼 지연시켜 이전 값이 사용되도록 한다.

52. 52 A simple Memory Model - text library IEEE; use IEEE.std_logic_1164.all; library BITLIB; use BITLIB.bit_pack.all; entity RAM6116 is port(Cs_b, We_b: in bit; Address: in bit_vector(7 downto 0); IO: inout std_logic_vector(7 downto 0)); end RAM6116; architecture simple_ram of RAM6116 is type RAMtype is array(0 to 255) of std_logic_vector(7 downto 0); signal RAM1: RAMtype:=(others=>(others=>'0')); -- Initialize all bits to '0' begin process begin if Cs_b = '1' then IO <= "ZZZZZZZZ";-- chip not selected else if We_b'event and We_b = '1' then -- rising-edge of We_b RAM1(vec2int(Address'delayed)) <= IO; -- write wait for 0 ns;-- wait for RAM update end if; if We_b = '1' then IO <= RAM1(vec2int(Address)); --read else IO <= "ZZZZZZZZ"; --drive high-Z end if; wait on We_b, Cs_b, Address; end process; end simple_ram;

53. 53 SRAM data sheet 분석

54. 54 SRAM data sheet 분석 - Overview

55. 55 SRAM data sheet 분석 – Pin & Block

56. 56 SRAM data sheet 분석

57. 57 SRAM data sheet 분석

58. 58 SRAM data sheet 분석

59. 59 SRAM data sheet 분석

60. 60 SRAM data sheet 분석

61. 61 SRAM data sheet 분석