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CSCM (Thermal Amplifier) Sequence and detailed planning 07/10/2011 M.Solfaroli Thanks to: K.Brodzinski, G.D’Angelo, M.Koratzinos, M.Pojer, R.Schmidt, J.Steckert,

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Presentation on theme: "CSCM (Thermal Amplifier) Sequence and detailed planning 07/10/2011 M.Solfaroli Thanks to: K.Brodzinski, G.D’Angelo, M.Koratzinos, M.Pojer, R.Schmidt, J.Steckert,"— Presentation transcript:

1 CSCM (Thermal Amplifier) Sequence and detailed planning 07/10/2011 M.Solfaroli Thanks to: K.Brodzinski, G.D’Angelo, M.Koratzinos, M.Pojer, R.Schmidt, J.Steckert, H.Thiesen, A.Verweij

2 07/10/20112 General layout CSCM workshop - M.Solfaroli The RB power converter will be used (in a special configuration) to power the RB circuit, then the RQD/F. These 2 circuits will be tested as a unique line. Preparation Test execution Restoring normal configuration Re- commissioning (see Mirko’s) 3 circuits to be tested: o RB o RQD o RQF

3 07/10/20113 Modification: PC CSCM workshop - M.Solfaroli RB converter needs to provide 300 V: o Install new 2MW power converters for the tests o No power converters available o Heavy installation work o Connect in series both RB power converters (UAx3 and UAx7) o 500 m between the both power converters o How to control the converters (separate control) o Modify the MB power converter o 2 bridges in // to reach 13kA o 2 bridges in series to reach 380V See Hugues’

4 07/10/20114 Modification QPS + EE CSCM workshop - M.Solfaroli o EE system: o Short circuit to exclude the system from the circuits in order to avoid V spike whenever the quench loop is open and the current is extracted o QPS: o Exchange of all BS board (the old ones will be left close to the rack in dedicated box and labeled) o Muting of the old QPS system and plugging the relative cables o Muting of the global busbar detector o Threshold estimation and load See Jen’s

5 07/10/20115 Modification: PIC CSCM workshop - M.Solfaroli o Swapping some interlock cables to allow powering the RQD/F circuits with the RB power supply o As the test will be carried out at 20 K a masking of the cryo conditions is needed o Deactivation of the global protection mechanism to allow powering while other circuits are not in condition

6 07/10/20116 Preparation timeline CSCM workshop - M.Solfaroli (PC lock and QHPS off are considered to take place at the beginning of Xmas Stop for all circuits) RB PC configuration preparation – 2 weeks BS board exchange – 3 days Old QPS and global BB detector muting – 1 day EE strap – ½ day PIC cabling modification - ½ day DC cables disconnection (on DFB) RB, RQD, RQF – ½ day ElQA at reduced voltage (360/600 V) on RB, RQD, RQF – 1 day DC cables connection (on DFB) and PC unlock – ½ day Tests – minimum 6 days

7 07/10/20117 Restoring timeline CSCM workshop - M.Solfaroli Tests – 6 days PC lock and DC cables disconnection (on DFB) (RB, RQD, RQF and spool pieces) – ½ day BS board exchange – 3 days Old QPS and global BB detector un-muting – 1 day EE strap removal – ½ day PIC cabling re-setting – ½ day PC special configuration removal – 2 weeks ElQA (RB, RQD, RQF, spool pieces) – 1 day DC cables connection (on DFB) (RB, RQD, RQF, spool pieces) – ½ day QHPS switching on + IST first step – 1 day Re-commissioning of the circuits – 4 days (no difference wrt other sectors)

8 07/10/20118 Preparation/restoring planning CSCM workshop - M.Solfaroli 2 weeks for preparation 2 weeks for removal 7 days of test

9 07/10/20119CSCM workshop - M.Solfaroli Test baseline  IST on all QPS magnets - 4 hours  PCC – 1 (0.5) day  V ramp, current ramp to 1 kA, 60 s plateau, ramp down – 30 min:  Check that functionality is correct (all diodes open)  Check signal from all boards is present and correct  Setting the threshold values  Establishing and loading the threshold on the boards – 2 h

10 07/10/201110CSCM workshop - M.Solfaroli Test baseline  Reading the threshold values to make sure they have been correctly loaded – 5 min  V ramp, current ramp to 5 kA (4 kA for RQDF), 60 s plateau, ramp down – 30 min  The first thermal run-away can occur at this stage  V ramp, current ramp to 6 kA (5 kA for RQDF), 60 s plateau, ramp down – 30 min NB Thermal runaway is likely to happen even if all splices are good for 5 TeV  V ramp, current ramp to 6 kA (5 kA for RQDF), 60 s plateau, ramp down to check nothing has been compromised – 30 min

11 07/10/201111CSCM workshop - M.Solfaroli Cryogenic considerations  Cryogenic recovery time estimation:  2h from 1 kA  4h from 5(4) kA  5h from 6(5) kA  The time estimation is difficult as the He is in gas state and the estimation of the heat released into the cryogenic system is tricky. Moreover, the system will be used in non standard conditions.  Temperature required for the test is 20 ± 10 K  The homogeneity of the temperature over the sector can be ensured in a range of 2 K

12 07/10/201112CSCM workshop - M.Solfaroli Test timeline STEP - RBTime 1 RB PIC12 h 2PCC1 day 3RB test @1 kA½ h 4Recovery2 h 5Threshold loading + check2 h 6RB test @5 kA½ h 7Recovery4 h 8RB test @6 kA½ h 9Recovery5 h 10RB test @6 kA½ h 11 Recovery5 h STEP – RQDFTime 1RQDF PIC12 h 2PCC1/2 day 3RQDF test @1 kA½ h 4Recovery2 h 5Threshold loading + check2 h 6RQDF test @4 kA½ h 7Recovery4 h 8RQDF test @5 kA½ h 9Recovery5 h 10RQDF test @5 kA½ h 11 Recovery5 h nQPS IST – 4 hours Configuration change~ 1day

13 07/10/201113CSCM workshop - M.Solfaroli Test planning 3 days per circuit + 1 day for changing the configuration

14 07/10/201114CSCM workshop - M.Solfaroli Initial strategy S12 – 23 - 34 – 45 Good for >=4.5TeV? 3.5/4 TeV Estimated delay = D weeks (test + HWC) 3.5/4 TeV Estimated delay = D weeks (test + HWC) P 5 = probability to find bad splice for 5TeV P 5 > X ? S78 – 81 Good for >= 4.5 TeV? S56 - 67 Good for >= 4.5 TeV? NO (D = 4) NO (D = 6) NO (D = 8) YES NO 4.5 or 5 TeV Estimated delay = 10 weeks (test + HWC + BC) 4.5 or 5 TeV Estimated delay = 10 weeks (test + HWC + BC) YES (D = 4)

15 07/10/201115CSCM workshop - M.Solfaroli Type test  CSCM test was born as a global test to be done in all sectors of the LHC to try to increase the LHC operational Energy  We then realized that the there would have been a strong impact on Xmas break activities and the physics production would have probably not start before probably beginning July  It was then decided that with a type test valuable experience to study the methodology and tools and improve them for later testing could be gained  It was decided to go for a type test during the Xmas stop in one sector

16 07/10/201116CSCM workshop - M.Solfaroli Test location SectCryo + planning availability Cryo considerationPlanning considerationDN200 S12Wk 6 + delayOKInstallation blindage in UJ13/17OK S23Wk 4OKNO S34Wk 6 + delay (~5 days)OK S45Wk 7 Fragile leak in the QRL. To be avoided. CablingPartial S56Wk 6 + delayOK S67Wk 5 + delayOKCablingOK S78Wk 3-4OKCabling R2E + termo switchesNO S81Wk 3-4OKCabling R2E + termo switchesNO Due to the constraints of the cryo maintenance schedule and the timing needed to stabilize the sector before the Xmas holidays it is not possible to have one sector available before Xmas

17 07/10/201117CSCM workshop - M.Solfaroli Full test This is an exercise!!  All cryo conditions at the same time  No time for establishing cryo conditions has been allocated  1 week for both EPC and QPS  2 teams for EPC as well as for QPS  1 week testing  No time for all removal nor re- commissioning has been considered  BS boards for 3 sectors  Ending with 59 days

18 07/10/2011CSCM workshop - M.Solfaroli18 Safety: access during powering Access rules during powering tests are described in the document “Access and Powering Conditions for the LHC Superconducting Circuits”, EDMS No. 1001985 POWERING PHASE I  Energy stored in superconducting magnets < 100 kJ  Access limited to the tunnel (no patrol needed)  Access possible to UAs and experiments POWERING PHASE II  Energy stored in superconducting circuit > 100 kJ  Access forbidden in tunnel, UAs and adjacent sectors (“Access Restrictions in LHC and SPS during LHC Powering Phase II” EDMS No. 1010617)

19 07/10/2011CSCM workshop - M.Solfaroli19 Safety: access during CSCM DRAFT GENERAL CONSIDERATIONS  Energy in the circuits > 100 kJ  No Energy is stored in the magnets - time constant for energy extraction extremely smaller (1-2 s) ELECTRICAL RISKS  High voltage applied  Protection in place on DFBs  All persons accessing has to have the H0/B0 habilitation CRYOGENIC RISKS  He in gas status (in the worst case the release is limited and it will not have impact on neighboring sectors of the LHC)

20 07/10/2011CSCM workshop - M.Solfaroli20 Safety: responsibility ?? o Safety measures to be put in place are still under discussion o First considerations seem to indicate that rules applied to Phase I powering could be sufficient to ensure personnel safety o An EDMS document has to be released once the rules are finalized o We have involved in the discussion safety people from different department o Who is in charge to put the final stamp on the solution? o Who is responsible for leading the test in the CCC (OP, TE, …)?


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