1. Jorgen Christiansen, CERN PH-ESE 1

2.  Finally officially part of CERN grey book: Recognized experiments  Spokes persons and Institute chair elected  Pending requests for membership: Milano, Prague, (OMEGA)  IB meetings have started: ~2 times per year  RD53 workshop: April 10 -11at CERN  MOU in the pipeline (Lino) ◦ First draft circulated among IB chair, SPs, MOU experts ◦ Next version to be circulated in RD53 IB  Working groups have started regular meetings ◦ 3 WG conveners assigned: Radiation, Analog, Simulation ◦ 2 WGs bootstrapped by SPs: Top, IP ◦ 1 WG not yet started: I/O  Some RD53 institutes have gotten funding for RD53 activities (e.g. INFN) 2

3. 3 WGDomain WG1Radiation test/qualification: M. Barbero, CPPM Coordinate test and qualification of 65nm for 1Grad TID and10 16 neu/cm 2 Radiation tests and reports. Transistor simulation models after radiation degradation Expertise on radiation effects in 65nm WG2Top level: (M. Garcia-sciveres, LBNL) Design Methodology/tools for large complex pixel chip Integration of analog in large digital design Design and verification methodology for very large chips. Design methodology for low power design/synthesis. Clock distribution and optimization. WG3Simulation/verification framework: T. Hemperek, Bonn System Verilog simulation and Verification framework Optimization of global architecture/pixel regions/pixel cells WG4I/O + (Standard cell): Convener to be nominated Development of rad hard IO cells (and standard cells if required) Standardized interfaces: Control, Readout, etc. WG5Analog design / analog front-end: V. Re, Bergamo/Pavia Define detailed requirements to analog front-end and digitization Evaluate different analog design approaches for very high radiation environment. Develop analog front-ends WG6IP blocks: ( J. Christiansen, CERN) Definition of required building blocks: RAM, PLL, references, ADC, DAC, power conversion, LDO,, Distribute design work among institutes Implementation, test, verification, documentation

4.  Unprecedented hostile radiation: ◦ 1Grad, 10 16 Neu/cm 2  On-going activities: ◦ CPPM: Radiation of CERN test structures to 1Grad, Annealing studies, Cold radiation ◦ CERN: CERN rad test structures, radiation tests to ~200Mrad, X-ray machine, 1Grad on Clic pix chip ◦ Fermilab: New 65nm test structures, Preparing radiation tests with Cobolt source ◦ LBNL/CPPM: IBM 65nm ◦ Perugia: Expertise on radiation testing (space)  To come: ◦ Padova: Radiation tests with their X-ray machine (cold ?) ◦ Other ?  Defining appropriate radiation protocol compatible with cold pixel operation  First results: Major effects above ~200Mrad and some mysteries ◦ NMOS: Vt shift: 300 – 250mv, Drive current: -70% - -30% ◦ PMOS: Vt shift: 120 – 450mv, Drive current: -100% - -60% ◦ http://indico.cern.ch/conferenceDisplay.py?confId=293582 http://indico.cern.ch/conferenceDisplay.py?confId=293582 ◦ Annealing scenario critical !.  Alternative technologies will be evaluated: ◦ Get PCM from other MOSIS runs: IBM 65 (LBNL), Other 65nm ? ◦ Dedicated test chips: TSMC 40nm ?, ST 65 ?, Other ? 4

5. 5 M. Menouni, CPPM Why is 240/60 the worst ? Not systematic with size !

6. 6 M. Menouni, CPPM Most likely acceptable for our pixel digital circuits (relatively low speed)

7. 7 M. Menouni, CPPM Why is 240/60 the worst ? Transistor died before end Reverse annealing ! And quite severe

8. 8 M. Menouni, CPPM Acceptable for our pixel digital circuits ?

9.  ~30 IP blocks defined ◦ Specs not yet defined ◦ Multiple versions ? (radiation tolerance, low power, etc. ) ◦ Some may not be needed (depends on architecture/implementation)  Converging on who makes what  Each IP will have an organizing (O) institute with possible additional participants (P)  Needs to define how to make IPs appropriately ◦ Specs, Layout, radiation, P&R, Simulation model, Documentation, database, etc.  Potential synergies ◦ CERN 65m tech support: Bandgap, ADC, RAM, ADC, digital libraries, etc.  Limited to 200Mrad, OK for all except CMS/ATLAS pixels !. ◦ CLIC pix: Very different requirements (part of RD53)  Existing design blocks can be used as starting point for ATLAS/CMS ◦ LP-GBT: E-links, PLLs, etc.  LP-GBT project has not yet started officially ◦ CMS OT: MPA chip (CERN, Bergamo-Pavia, ?) ◦ Other ? 9

10. 10 CountryDE FRUSNLIT - INFNUSFRUK USUSCZ Group Bonn CERN CPPM FNL NIKHEF Bari Pav/ Berg (Milano) Padova Pisa Torino LBNL LPNHE RAL Santa Cruz (Prague) (AIDA)Comments/conclusions ANALOG: Coordination with analog WG Low noise Pre-amp – shaper B (clicpix) B (CMS MPA)BA A AA A A Analog WG, Multiple options Charge measurement (TOT or ADC) A (ADC)B (clicpix) A (ADC)A BA AA A C Analog WG, Multiple options Calibration pulse generator Analog WG, missing volunteers Temperature sensor. A B B C BCPPM Radiation sensor B C B C CPPM, INFN(Torino) HV leakage current sensor. B C C CPPM Band gap reference A (65nm kit)A A A B LAPP, CPPMCERN, CPPM, NIKHEF, INFN(Pavia) Self-biased Rail to Rail analog buffer B B B C C A B RAL MIXED 4-8 bit threshold DAC B (clicpix) B (CMS MPA)C BA A A B Integral part of analog FE (analog WG) 8 – 12 bit biasing DAC B (clicpix) B (CMS MPA)C A BOMEGA, CPPM, PaviaBari 10 - 12 bit slow ADC for monitoring A (65nm kit)A A CERN, OMEGA, LAPPCERN, CPPM, INFN (Bari) PLL for clock multiplication AA (GBT) B ABB BA CrakowBonn, CERN, INFN (Padova), Santa Cruz (Voltage controlled Oscillator) B B AAA Needed ?: INFN (Padova, Pisa, Torino) High speed serializer ( ~Gbit/s) AA (GBT)C A A AA ~1.2Gbits/s ?: Bonn, CERN, NIKHEF, INFN (Pisa), RAL, Santa Cruz Clock recovery and jiter filter AB (GBT) B B Needed ?: Bonn Programmable delay AB (GBT) B B Bonn DIGITAL SRAM for pixel region BB (65nm kit) A A Milano Santa Cruz, INFN (Milano) SRAM/FIFO for EOC. BA (65nm kit) A B A CERN, Santa Cruz, INFN (Milano) EPROM/EFUSE BB (GBT)C Bonn, CERN DICE storage cell ? B A A B CB CPPM, INFN (Milano) LP Clock driver/receiver B B B Bonn, INFN (Pavia), RAL (Dedicated rad hard digital library) B C B CC Mi, LAPP, CPPM, LPNHEOnly if required: Bonn, INFN (Pisa) (compact mini digital library for pixels) B B CC Only if required: Bonn, CPPM IO: IO WG ? Basic IO cells for radiation BA (65nm kit) C CERN Low speed SLVS driver ( <100MHz) AB (GBT) A AA C B Bonn, Pavia, Krakow Bonn, INFN (Pavia, Pisa, Torino) High speed SLVS driver (~1Gbits/s) AB (GBT) A AA CC BBonn, INFN (Pavia, Pisa, Torino) SLVS receiver AB (GBT) A B C BBonn C4 and wire bond pads BB (GBT)C C C Bonn, CERN (IO pad for TSV) BCC C C Needed ?: Bonn Analog Rail to Rail output buffer B B C C Bonn, CPPM Analog input pad B C Bonn (pixel bump pad) Integral part of analog FE POWER LDO(s) C (clicpix) C (gen pow.)C A AA C NIKHEF, INFN (Pisa, Torino) Switched capacitor DC/DC B (gen pow.) A C LBNL Shunt regulator for serial powering B NIKHEF Power-on reset Missing volunteers Power pads with appropriate ESD BA (65nm kit)C C CERN SOFT IP: Coordination with IO WG Control and command interface A (GBT) A A B CERN, INFN (Bari, Pisa) Readout interface (E-link ?) A (GBT) A A B CERN, INFN (Bari, Pisa) Notes: A: High interest B: Medium interest C: Low interest INFN institutes (Bari, Pavia, Milano, Padova, Pisa, Torino) organized within INFN project GBT in CERN collum refers to fact that 65nm LPGBT will need same/similar IP block CMS MPA: Macro pixel ASIC in 65nm for CMS inner track trigger detector IP blocks made by CLICpix and CMS MPA can possibly be transferred to other groups for radiation testing to 1Grad and required improvements/changes

11. 11

12.  Front-end specifications being defined  Different FE architectures will be evaluated, designed and prototyped: ◦ Noise as function of capacitance ◦ Power ◦ Resolution: TOT, ADC ◦ Time walk ◦ Dead time ◦ Effective threshold ◦ Area ◦ Radiation tolerance ◦ Etc.  To be defined how work across groups and different FE architectures can be best optimized/shared for our final goal(s). 12

13.  Simulation framework in System Verilog + UVM ◦ CERN, Perugia ◦ Seems sufficiently flexible and covers: TLM – Behavioural - RTL – Gate level ◦ Simulation speed could be an issue but does not seem to be a show stopper  Benchmarking with FEI4 seems OK ◦ Collaboration with Timepix- Velopix (using same tool set)  Other tools/languages to be tried/evaluated ?. ◦ Lack of manpower  Generation of realistic hits: Sensor types, rates, clusters shapes, different locations, etc. ◦ From within SV: Good for fast check of typical and extreme cases ◦ From Geant 4 simulations: Check with “realistic” physics data ◦ CERN-LCD will start to work on this. Other pixel/simulation experts welcome.  Defining interface of pixel chip: hits, clock, readout, trigger, control, etc. ◦ Simulation framework: TLM based (software oriented) ◦ Pixel chip: Behavioural, RTL, Gate (TLM), (hardware oriented)  First case use: Evaluation of different latency buffer architectures ◦ Critical for CMS with long latency: 10-20us ◦ Cross check with statistical model ◦ Elia Conti, Perugia  Only few groups/people so far contributing to this WG. 13

14. 14 DUT PixelChip Flag Component Flag Monitor Readout Component Readout Monitor PixelChip Interfaces PixelChipHarness Clock and reset generator PixelChipEnv Stimuli Component HiLevel Generator Hit Driver Hit Monitor Trigger Driver Conformity Checker Trigger Monitor Hit Generator Trig_intf Hit_intfFlag_intf Readout_intf Class/TLM based Behavioural E. Conti

15.  Define appropriate schemes and tools to integrate complex mixed signal functions into large pixel chip ◦ Layout (e.g. Technology options, layer mapping), powering, noise coupling, Final design verification,  Discussions have started on what the major issues are and how to organize this  Architectures: ◦ Collect proposals for different alternative architectures.  Pixel regions: Size, shape, data buffering,,  Data transport in columns: shared bus, serial links,,  EOC: Buffering, Data merging, Data compression, track extraction,, ◦ Define how to evaluate these at top level for integration aspects, power, radiation, performance (simulation WG). 15

16.  Goals: ◦ Define standardized I/O interface of pixel chips ◦ Define and implement I/O blocks  Some overlap with IP blocks (hard and soft IPs) Standardized pixel chip interfaces also allows to standardize pixel chip test systems  Convener: To be assigned 16

17.  2014: ◦ Release of CERN 65nm design kit: Very soon ! ◦ Detailed understanding of radiation effects in 65nm  Radiation test of few alternative technologies.  Spice models of transistors after radiation/annealing ◦ IP block responsibilities defined and appearance of first IP designs and prototypes ◦ Available simulation framework with realistic hit generation and auto-verification. ◦ Alternative architectures defined and efforts to simulate and compare these defined ◦ Common MPW submission 1: First versions of IP blocks and analog front-ends  2015: ◦ Common MPW submission 2: Near final versions of IP blocks and FEs. ◦ Final versions of IP blocks and FEs with tested prototypes, documentation, simulation, etc. ◦ IO interface of pixel chip(s) defined in detail ◦ Global architecture defined and extensively simulated ◦ Common MPW submission 3: Final IPs and Fes, Small pixel array(s)  2016: ◦ Common engineering run submission: Full or reduced sized pixel arrays(s). ◦ Pixel chip tests, radiation tests, beam tests,,  2017: ◦ Separate or common ATLAS – CMS full – final pixel chip submissions. 17