Download presentation
Presentation is loading. Please wait.
1
Chapter 3 Wafering and ULSI Process
2
Source:Solid State Technology
Semiconductor roadmap Source:Solid State Technology
3
( Silicon wafering process )
Introduction Manufacturing Process Application
4
(single side grinding) (single side polishing)
Introduction / Manufacturing Process / Application polysilicon : 고순도 다결정 실리콘 pulling :폴리실리콘을 방향성을 가지는 단결정으로 성장 ingot : 단결정 실리콘 성장 괴 ingot grinding : 단결정 실리콘 성장 괴의 원통 외주 연삭 가공 ingot grinding : 단결정 실리콘 성장 괴의 OF 연삭 가공 etching : 웨이퍼의 표면 변질층 제거 double side lapping : 웨이퍼의 양면 래핑 가공 edge grinding : 웨이퍼의 에지 연삭 가공 double side grinding (single side grinding) : 웨이퍼의 양면 연삭 가공 slicing : 단결정 실리콘 성장 괴의 웨이퍼 절단 가공 double side polishing (single side polishing) : 웨이퍼의 양면 연마 가공 epi-layer growth : 소자 집적층을 위해 Si layer 성장 prime wafer : 소자 집적을 위한 웨이퍼
5
Wafer Diameter and Semiconductor Generation
Introduction / Manufacturing Process / Application Wafer Diameter and Semiconductor Generation Relationship between Wafer Diameter and Semiconductor Generation Chip Size Effective Chip Yield per Wafer Year
6
Specifications for 8 inch Si Wafers
Introduction / Manufacturing Process / Application Specifications for 8 inch Si Wafers ITEMS SPECIFICATION Test Method Growth CZ (Czochralski Growth) STM F 613 Diameter 200 0.2mm Type P, P+ / Boron Resistivity cm N / Phosphorus Resistivity cm N+ / Antimony Resistivity cm STM F 42 STM F 673 Crystal Orientation ( ) STM F 26 Orientation Flat / Notch SEMI-STD or Custom STM F / F 671 Flatness Global TTV Average 1.3µm Global TIR Average 0.8µm STIR (2020mm) Average 0.4µm ASTM F 657 ASTM F 1530 SEMI-STD M1 Warp / Bow Average µm ASTM F657 / F534 Oxygen 10-17 ppma (Old ; 20-35) STM F 1188 Metallic Impurity 5 E10 aoms/cm3 ICP - MS Backside Treatment Soft Damaged or Enhanced Gettering Particle > µm EA/Wafer > µm EA/Wafer Particle Counter
7
Required Breakthrough Technologies for 450mm Wafer
Introduction / Manufacturing Process / Application Required Breakthrough Technologies for 450mm Wafer Crystal Growth Technologies Development of a New Mechanism to Suspend very Heavy, Single Silicon Crystals instead of Necking High Crystalline Quality by Designing Optimal Thermal History during CZ Growth Design and Manufacture of 900mm and Larger Quartz Crucible of High Purity and Long Life for Crystal Growth Safety Precautions to Prevent Steam Explosions Caused by Leakage of heavily Charged Silicon Melt Wafer Shaping Technologies Low-Warp, Low-Taper Slicing Technology High-Flatness, Lapping/Grinding and Polishing Technology High Purity, Cleaning Technology
8
Required Breakthrough Technologies for 450mm Wafer
Introduction / Manufacturing Process / Application Required Breakthrough Technologies for 450mm Wafer Inspection and Evaluation Technologies High Sensitivity Particle Detection Mechanism New Algorithm for Flatness Measurement Evaluation and Analysis Methods for Surface and Subsurface Measurement Epitaxial Growing Technologies High Uniform Growth of Super-thin Epitaxial Layer Low Temperature Epitaxial Growth Hiph-Purity and Defect
9
Introduction / Manufacturing Process / Application
Polycrystal Creation MEMC and Mitsubishi Materials Silicon create raw polycrystalline silicon by mixing refined trichlorosilane with gas in a reaction furnace and allowing the polycrystalline silicon to grow on the surface of electrically heated tantalum hollow metal wick. They then refine the polycrystalline silicon tubes by dissolving them in hydrofluoric acid and produce polysilicon ingots. Because polycrystalline silicon has randomly oriented crystallites, it doesn't have the electrical characteristics necessary for semiconductor device fabrication. It must first be transformed into single crystal silicon using a process called .
10
Crystal Pulling Introduction / Manufacturing Process / Application
Crushed high-purity polycrystalline silicon is doped with elements like arsenic, boron, phosphorous or antimony and melted at 1400° in a quartz crucible surrounded by an inert gas atmosphere of high purity argon. The melt is cooled to a precise temperature, then a "seed” of single crystal silicon is placed into the melt and slowly rotated as it is "pulled" out. The surface tension between the seed and the molten silicon causes a small amount of the liquid to rise with the seed and cool into a single crystalline ingot with the same orientation as the seed. The ingot diameter is determined by a combination of temperature and extraction speed. Most ingots produced today are 150mm (6") and 200mm (8") diameter, but Komatsu Silicon America, MEMC, Mitsubishi Silicon America and Shin-Etsu Handotai America are developing 300mm (12") and 400mm (16") diameter ingots.
11
Wafer Slicing Ingot Characterization Wafer Slicing
Introduction / Manufacturing Process / Application Wafer Slicing Ingot Characterization Primary Flat Secondary Single crystal silicon ingots are characterized by the orientation of their silicon crystals. Before the ingot is cut into wafers, one or two "flats" are ground into the diameter of the ingot to mark this orientation. Wafer Slicing After characterization, we slice the ingot into individual wafers with a precision "ID Saw,” so named because the cutting edge of the blade is on the inside. This type of saw is used because the blades have less "kerf" and produce a more precise and controllable cut and a flatter wafer. From 1994, Si wafer makers introduced the use of wire saws
12
Continuous Wafer Heat Treatment
Introduction / Manufacturing Process / Application Edge Beveling Edge beveling smoothes out the peripheral edges of the wafer. Wafer makers have improved on traditional edge beveling methods by implementing a chemical beveling and polishing that leads to a marked improvement in quality. Continuous Wafer Heat Treatment Oxygen donor(Silicon and oxygen compounds) cause incorrect resistivity values during the intentional doping process, and must be annihilated using a continuous wafer heat treatment (CWHT) where the wafers are heated quickly to high temperatures in order to annihilate the donors. They are then cooled again at a similar high speed to prevent the donor regeneration. Wafer Gettering Wafer gettering process is a process for eliminating metal impurities such as iron and copper from the wafer surface by diffusing a contaminant into the subsurface. As the silicon matrix is very stable, excess oxygen will precipitate to from irregular fields and thereby create free space in which the impurities can be trapped. In 1988, Polysilicon Chemical Vapor Deposition(CVD) was introduced as an effective gettering source. Polycrystal could be placed at the backside of the silicon wafer to attract impurities into the irregular space.
13
Lapping Process Etching Process
Introduction / Manufacturing Process / Application Lapping Process The sliced are mechanically lapped using a counter rotating lapping machine and an aluminum oxide slurry. This flattens the wafer surfaces, makes them parallel and reduces mechanical defects like saw markings. Etching Process The Surface of the lapped wafers are then etched to remove any remaining micro cracks or surface damage introduced by the alumina abrasive in the previous lap-stage. Etching is done chemically using a corrosive mixture of nitric acid and glacial acetic acid solution. This acidic surface dissol -ving technique is preferred in Japan over the more caustic U.S. etching method which uses a sodium hydroxide(NaOH) base solution.
14
Etching Mechanism Silicon Etching SiO2 Etching
Introduction / Manufacturing Process / Application Etching Mechanism - Mainly Dependent on Ionic Strength, Solution pH, and Etchant Solution, Bubble - Not Directly Soluble in Etchant Solution ( Necessary to Change the Material to be Etched from a Solid to a Liquid or a Gas ) Step 1. Etchant Movement to the Wafer Surface Step 2. Chemical Reaction with Exposed Film ( that produce soluble byproducts ) Step 3. Reaction Products Movement away from Wafer Surface Polishing Silicon Etching 3Si + 4HNO SiO2 + 4NO + 2H2O 3SiO2 + 18HF H2SiF6 + 6H2O 3Si + 4HNO3 + 18HF H2SiF6 + 4NO + 8H2O SiO2 Etching SiO2 + 6HF H2 + SiF6 + 2H2O BHF(HF with a Buffering Agent) NH4F NH3 + HF The Etch Rate of Silicon in HF and HNO3
15
Wafer Surface Conditions
Introduction / Manufacturing Process / Application Etching Parameters Removal Rate Wafer Surface Conditions Wettability - Hydrophobic / Hydrophilic Surface Damage - Sawed / Lapped / Ground / Polished Material Parameters Orientation - (100) / (111) / (110) Doping Concentration - > 1E19 / < 1E19 Process Conditions Temperature Etching Reagent - KOH / NaOH / ED - Fresh / Used Additive - Surfactant / Water / Gas Concentration - c > or = or < Peak Point Mechanical Support - US/MS / Oscillation / Stirring Gas Bubbling Equipment Temperature Stability - Recirculation / Wafer Distance Temperature Control / Bath Size Concentration Stability - C Control / Recirculation Sub-dosing System
16
Wafer Grinding Technology
Introduction / Manufacturing Process / Application Wafer Grinding Technology Grinding Lapping Principle Grain Mechanical Damage Automation Removal Speed Surface Roughness Fixed Large Applicable > 200um/min Rmax < 0.1um Loose Small Difficult < 2um/min Rmax < 1.0um Wheel Wafer Lap Lapping Fluid
17
Schematic View of Wafer Grinding
Introduction / Manufacturing Process / Application Schematic View of Wafer Grinding Wafer Vacuum Chuck wwp : wafer rotation FN FT n t r ww : wheel Wheel Infeed
18
Grinding Mechanism in Brittle Materials
Introduction / Manufacturing Process / Application Grinding Mechanism in Brittle Materials Factors Affecting Material Removal in Finishing of Brittle Materials Domain Dislocation Micro-Crack Crack, Void Grain Boundary Layer Atom I II III IV Interstitial Atom Vacancy 10 -7 10 -6 10 -3 10 -4 10 -2 10 -1 10 0 Machining Unit, mm Domain I. Material removal is the order of a few atoms or molecules Chemical action enhanced by stress and temperature is important Domain II. The generation of dislocations prior to brittle fracture Domain III. Only dislocation (plastic deformation) Domain IV. Factors Affecting Deformation and Fracture of Materials (Yoshikawa) Defects due to cracks are the dominant factors in material removal
19
Okamoto Machine Tool Works, LTD
Introduction / Manufacturing Process / Application Rotary Surface Grinding Machine Okamoto Machine Tool Works, LTD Specification Model PRG-6DXNC PRG-8DXNC Table Size 600 800 Wheel Size 355(50Hz) / 305(60Hz) 50 127 Wheel Spindle Motor 7.5KW / 4P Z-Axis Stroke 250mm(50Hz) / 275mm(60Hz) Machine Net Weight 3000 kgf 3500 kgf
20
Okamoto Machine Tool Works, LTD
Introduction / Manufacturing Process / Application Dual Side Wafer Grinding Machine Okamoto Machine Tool Works, LTD Specification (SVG202MK) 12” Chuck Table Index Coarse Grinding Finish Loading Unloading Wafer Diameter ~300mm Grinding Wheel f 125~250mm Holding Chuck Vacuum Grind Spindles ~3600rpm Work Spindles ~1000rpm R/G Feed Rate ~30um/min F/G Feed Rate ~20um/min In-Situ Contact Thickness Gauge Rinse, Spin Dry Unit
21
Double Side Wafer Grinding Machine
Introduction / Manufacturing Process / Application Double Side Wafer Grinding Machine Cassette Measuring System Fixed Grinding Spindle Movable Grinding Holding Roller Transport system Wafer Diameter ~300mm Grinding Wheel f 200mm Wafer Holding 3P-Roller & Hydraulic Pressure Wheel Spindles ~5000rpm Work Spindles rpm X-Axis Resolution um In-Situ Contact Thickness Gauge Rinse, Spin Dry Unit Specification (HSD30NL, NACHI)
22
Chemical Mechanical Wafer Grinder
Introduction / Manufacturing Process / Application Chemical Mechanical Wafer Grinder TOKYO SEIMITSU Depth of damage less than 7µm Depth of damage less than 0.4µm Depth of damage less than 0.1µm Depth of Damage Observation by TEM Thinning Process Rough Grinding Fine Grinding Fine Polishing
23
Double Side Wafer Grinding Machine
Introduction / Manufacturing Process / Application Double Side Wafer Grinding Machine Straubaugh Programmable Technical Features (Model 7AF) Grind Spindles Linear Guide Coarse Grinding Fine Cassette 1 Cassette 2 Cassette 3 Cassette 4 Cassette Turrets Chuck ; Two 3 HP servo-controlled, variable-speed RPM direct drive air bearings. Rough Grind Feed Rate ; Three step, programmable µm/sec ; programmable dwell revolutions Force Controlled Grinding ; Grinding wheel will grind at feed rate until grinding force exceeds programmable force, then grinding force establishes removal rate Work Spindles ; Two brushless DC servo controlled variable speed 1-500rpm, direct drive air bearing spindles Rinse / Spin Station ; DI water rinse. Programmable rpm spin dry
24
Polishing Process Introduction / Manufacturing Process / Application
Next, the wafers are polished in a series of a combination chemical and mechanical polishing processes called CMP. This Chemical-Mechanical Polishing(CMP) is currently employed and involves both mechanical and chemical polishing mechanisms. Silica powder is dissolved in de-ionized water and controlled at a pH 10~11 with sodium hydroxide, and then fed onto the wafers which are simultaneously buffed by a peel and stick polishing pad of artificial leather. This method removes any remaining surface roughness and the combined effect of the mechanical and chemical approach ensures that there is no additional damage during the process. The polishing process usually involves two or three polishing steps with progressively finer slurry and intermediate cleanings using RO/DI water.
25
Schematic View of Chemical Mechanical Polishing
Introduction / Manufacturing Process / Application Schematic View of Chemical Mechanical Polishing
26
Demand of Wafer Surface Quality
Introduction / Manufacturing Process / Application Demand of Wafer Surface Quality 6 inch 8 inch Front Side : Polished Edge Side : Etched Back Side : Etched 8 inch Front Side : Polished Edge Side : Polished Back Side : Etched 12 inch 18 inch Front Side : Polished Edge Side : Polished Back Side : Polished
27
Wafer Cleaning Introduction / Manufacturing Process / Application
Most wafer manufacturers use a final cleaning method developed by RCA in 1970. The 3-step process starts with an SC1 solution (ammonia, hydrogen peroxide and RO/DI water) to remove organic impurities and particles from the wafer surface. Next, natural oxides and metal impurities are removed with hydrofluoric acid, and finally, the SC2 solution, (hydrochloric acid and hydrogen peroxide), causes super clean new natural oxides to grow up on the surface. Original RCA Cleaning Step 1 “Standard Clean 1 of SC-1” alkaline peroxide mixture consisting of 5 vol H2O + 1 vol H2O2 30% + 1 vol NH4OH 29%, followed by D.I. water rinse Effect wet oxidation removal of organic surface films and exposes the surface for desorption of trace metals (Au, Ag, Cu, Ni, Cd, Zn, Co, Cr, etc.) Keeps forming and dissolving hydrous oxide film Step 2 “Standard Clean 2 of SC-2” acid peroxide mixture consisting of 6 vol H2O + 1 vol H2O2 30% + 1 vol HCl 37%, followed by D.I. water rinse Dissolves alkali ions hydorxides of Al+3, Fe+3, Mg+2 Desorbs by complexing residual metal Leaves protective passivation hydrated oxide film
28
SEZ Spin Etcher Introduction / Manufacturing Process / Application
Single wafer wet process multi-process chamber with vertically arranged levels Independent chemical lines Low chemical and water High efficiency and short processing time Chuck with wafer floating on N2 cushion - The opposite side of the wafer is fully protected (the side not being processed) by the N2 cushion, thus reducing the number of overall production steps Unmatched repeatability Small footprint Excellent uniformity High selectivity Unmatched process repeatability Low particle defect density because of low particle counts and watermark prevention Significant impact on overall single process cycle Process adaptation to customer needs Schematic View of Spin Etcher
29
Spin Etching Equipment
Introduction / Manufacturing Process / Application Spin Etching Equipment Frontside Process Removal of Native and Sacrificial Oxides Thinning of Oxides with Superior Uniformity High Selective Removal of CVD Oxide Poly Removal of Poly Buffered LOCOS Poly Spacer Removal Silicon Structuring, max. 3µm depth(Isotropic Etch) Sidewall Polymer Removal Post CMP Cleaning Test Wafer Reclaim Backside Process Si Substrate Etch Film Removal Wafer Thinning after / instead of Grinding Stress Relief after Grinding Silicon Pre-polish after Wafer Slicing and Grinding Prior to Photolithography esp. 0.35µm Technology After Poly/Phosphorous Gettering Removal of Heavy Metals SEZ Spin Etcher Wet Master Series 303
30
Wafer Epitaxial Processing
Introduction / Manufacturing Process / Application Wafer Epitaxial Processing Wafer manufacturer use a process called epitaxy (EPI) to grow a layer of single crystal silicon from vapor onto a single crystal silicon substrate at high temperatures. Trichlorosilane or silicon tetrachloride and hydrogen are combined with either diborane or phosphine gas to act as dopants. The purpose of EPI growth is to create a layer with different, usually lower, concentration of electrically active dopant on the substrate. For example, an n- type layer on a p-type wafer. The purpose of EPI growth is to create a layer with different, usually lower, concentration of electrically active dopant on the substrate. For example, an n-type layer on a p-type wafer. Epitaxial processing equipment and the supporting process piping systems include a wide range of HPM UHP gas systems (including as trichlorosilane, silicon tetrachloride, hydrogen, diborane and phosphine) and automated high- purity chemical distribution systems.
31
Epitaxial Growth Introduction / Manufacturing Process / Application
In case crystal perfection or multi-layers with different resistivities is required by the customers, a thin single crystalline layer called epitaxial layer is grown on the surface of a polished wafer by CVD (chemical vapor deposition) process. Infra-Red Lamp Wafer Chamber Heating (ca 1200℃) SiHCl3 (G) + H2 (G) Adsorption of Si Disadsorption of Si Migration to Growth Site 1 2 3 Epitaxial Furnace Chemical Vapor Deposition (CVD) Method
32
Dielectric Isolated Wafer(DIW)
Introduction / Manufacturing Process / Application Dielectric Isolated Wafer(DIW) Active Wafer Handle Wafer V-groove Formation Oxidation (Deposition of Poly-X’tal) CVD Back Grinding & Polishing Bonding Heat Treatment Grinding & Polishing of Active Wafer An active wafer is oxidized after V-shaped grooves are formed on the surface for isolation. A polycrystalline silicon layer is then deposited on the surface by CVD (chemical vapor deposition) process. The active wafer is subsequently bonded with an oxidized handle wafer, and the following heat treatment makes the two wafers join together. The bonded wafer is then ground and polished on the active wafer side up to a certain thickness. 3D Structure of DIW Silicon Island Oxide Ditch Poly-X’tal Silicon Oxide Film Handle Wafer
33
Silicon On Insulator (SOI) Wafer
Introduction / Manufacturing Process / Application Silicon On Insulator (SOI) Wafer DBW Direct Bonded Wafer SIMOX Separation by Implantation Oxygen Si Wafer Oxygen Implantation Si Wafer Thermal Oxidation ; SiO2 Layer Bonding Si Wafer Heat Treatment Thinning of Si Layer Si Layer Si Wafer SiO2 Layer Si Wafer
Similar presentations
