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Chapter 2. Computer-System Structure Device controllers: synchronize and manage access to devices.

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Presentation on theme: "Chapter 2. Computer-System Structure Device controllers: synchronize and manage access to devices."— Presentation transcript:

1 Chapter 2

2 Computer-System Structure Device controllers: synchronize and manage access to devices.

3 Computer-System Operation  I/O devices and the CPU can execute concurrently.  Each device controller is in charge of a particular device type.  Each device controller has a local buffer.  CPU moves data from/to main memory to/from local buffers  I/O is from the device to local buffer of controller.  Device controller informs CPU that it has finished its operation by causing an interrupt.

4 Booting  (also known as booting up) is the initial set of operations that a computer system performs when electrical power is switched on.  Bootstrap program:( also known as Boot) Initialize all aspects of the system, e.g., CPU registers, device controllers, memory, etc. Load and run the OS  Operating system: run init to initialize system processes, e.g., various daemons, login processes, after the kernel has been bootstrapped.

5 Interrupt  is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution.  Type of Interrupts  hardware interrupt causes the processor to save its state of execution and begin execution of an interrupt handler.  e.g. services requests of I/O devices, hardware failure such as parity error and power failure  Software interrupts(also called a ‘trap’)  interrupt generated by executing an instruction is called software interrupt. are generally used to make system calls i.e. to request operating system to perform an I/O operation or to run a new program.  e.g. signals, invalid memory access, division by  zero, system calls, etc – (trap)

6 Common Functions of Interrupts  An interrupt transfers control to an interrupt service routine through the interrupt vector, which contains the addresses of all the service routines.  Interrupt architecture must save the address of the interrupted instruction. " Saved in registers, on system stack, etc.  During interrupt processing, incoming interrupts are disabled to prevent lost interrupts.  A trap is a software-generated interrupt caused either by an error or a user request.

7 Interrupt Handling  The operating system preserves the state of the CPU by storing registers and the program counter.  Determines which type of interrupt has occurred: ✦ polling (common with I/O interrupts/requests) ✦ vectored interrupt system  Separate segments of code determine what action should be taken for each type of interrupt

8 I/O Structure

9 I/O operation  a. CPU sets up specific controller registers within the controller.  b. Read: devices controller buffers memory Write: memory controller buffers devices c. Notify the completion of the operation by triggering an interrupt

10 I/O Types(Synchronous) ❧ After I/O starts, control returns to user program only upon I/O completion ❧ Upon issuing I/O request, user program waits for interrupt signaling I/O completion. " wait instruction idles the CPU until the next interrupt " wait loop (contention for memory access). ❧ At most one I/O request is outstanding at a time, no simultaneous I/O processing. ❧ No overlapping of I/O with processing.

11 Asynchronous I/O or non-blocking I/O Is a form of input/output processing that permitsinput/output other processing to continue before the transmission has finished.

12  is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit (CPU).  Release CPU from handling excessive interrupts!  Used for high-speed I/O devices able to transmit information at close to memory speeds.

13  Main memory – only large storage media that the CPU can access directly. - Processor can have direct access!  Secondary storage – extension of main memory that provides large nonvolatile storage capacity.

14  Volatile memory is computer memory that requires power to maintain the stored information.  Non-volatile memory is computer memory that can retain the stored information even when not powered.

15  rigid metal or glass platters covered with magnetic recording material Examples - floppy disks, magnetic recording tape, and magnetic stripes on credit cards

16 STORAGE HIERARCHY

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18 Performance of Various Levels of Storage

19  Registers, cache, and main memory are volatile.  All storage after main memory are non- volatile.  Caching: Check first cache memory if data not there go to main memory and copy it into cache under the assumption that there is a high probability that it will be needed again.  Data must be moved from secondary storage into main memory before use.

20  Data transfer from cache to CPU and registers is usually a hardware function with no operating system control.  Data transfer from disk to memory is usually controlled by the operating system.  Cache Coherency and Consistency is the state that exists in a multiprocessor system, when any shared data is held by 2 or more caches, and no 2 caches hold different values of such a shared data simultaneously.

21 Storage Hierarchy  Storage systems organized in hierarchy.  Speed  Cost  Volatility  Caching – copying information into faster storage system; main memory can be viewed as a last cache for secondary storage.

22 Cache

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24  Pronounced cash, a special high- speed storage mechanism. It can be either a reserved section of main memory or an independent high-speed storage device. Two types of caching are commonly used in personal computers: memory caching and disk caching.storagemain memorystorage devicepersonal computers  A memory cache, sometimes called a cache store or RAM cache, is a portion of memory made of high-speed static RAM (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory. Memory caching is effective because most programs access the same data or instructions over and over. By keeping as much of this information as possible in SRAM, the computer avoids accessing the slower DRAM.RAM cachememorystatic RAMdynamic RAMDRAMprogramsaccessdatainstructions computer

25  Disk caching works under the same principle as memory caching, but instead of using high- speed SRAM, a disk cache uses conventional main memory. The most recently accessed data from the disk (as well as adjacent sectors) isstored in a memory buffer. When a program needs to access data from the disk, it first checks the disk cache to see if the data is there. Disk caching can dramatically improve the performance of applications, because accessing abyte of data in RAM can be thousands of times faster than accessing a byte on a hard disk.disk cachedisksectorsstoredapplicationsbyteRAMhard disk

26  When data is found in the cache, it is called a cache hit, and the effectiveness of a cache is judged by its hit rate. Many cache systems use a technique known as smart caching, in which the system can recognize certain types of frequently used data. The strategies for determining which information should be kept in the cache constitute some of the more interesting problems in computer science.systemscomputer science

27 Hardware Protection Goal: Prevent errors and misuse!

28 Hardware Protection  Dual-Mode Operation  I/O Protection  Memory Protection  CPU Protection

29 Dual-Mode Operation

30  Protection is needed for any shared resource.  Sharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly.  Provide hardware support to differentiate between at least two modes of operations.  User mode – execution done on behalf of a user.  Monitor mode (also supervisor mode or system mode) – execution done on behalf of operating system.

31  Mode bit added to computer hardware to indicate the current mode: monitor (0) or user (1).  At system boot time, the hardware starts in monitor mode. The O.S. is then loaded, and starts user processes in user mode.  Whenever, an interrupt occurs, the hardware switches from user mode to monitor mode.  Whenever, the O.S. gains control of the computer, it is in monitor mode.

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33 I/O Protection

34  All I/O instructions are privileged instructions.  Must ensure that a user program could never gain control of the computer in monitor mode(i.e., a user program that, as part of its execution, stores a new address in the interrupt vector).

35 Memory Protection

36  Must provide memory protection at least for the interrupt vector and the interrupt service routines. In order to have memory protection, add two registers that determine the range of legal addresses a program may access:  Base register – holds the smallest legal physical memory address.  Limit register – contains the size of the range Memory outside the defined range is protected.

37 CPU Protection

38  Prevent user programs from sucking up CPU power!  Timer – interrupts computer after specified period to ensure operating system maintains control.  Timer is decremented every clock tick.  When timer reaches the value 0, an interrupt occurs.  Timer commonly used to implement time sharing.  Time also used to compute the current time.  Load-timer is a privileged instruction.

39  System calls provide the interface between a running program and the operating system.  Generally available as assembly-language instructions.  Languages defined to replace assembly language for systems programming allow system calls to be made directly (e.g., C, Bliss, PL/360).  Three general methods are used to pass parameters between a running program and the operating system:  Pass parameters in registers.  Store the parameters in a table in memory, and the table address is passed as a parameter in a register.  Push (store) the parameters onto the stack by the program, and pop off the stack by the operating system.

40 Computer Structure Network Structure

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51 THE END


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