CISC 879 : Advanced Parallel Programming Vaibhav Naidu Dept. of Computer & Information Sciences University of Delaware Dark Silicon and End of Multicore Scaling Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger

CISC 879 : Advanced Parallel Programming Outline Introduction Motivation Models: 1. Device Scaling Model 2. Core Scaling Model 3. Multicore Scaling Model Model Combinations Summary Conclusion

CISC 879 : Advanced Parallel Programming Introduction Moore’s Law: Doubling of transistors every 18 months. Dennard scaling: As transistors get smaller, their power density stays constant. Moore’s law coupled with Dennard scaling has resulted in commensurate exponential performance increase

CISC 879 : Advanced Parallel Programming Introduction In recent years, Dennard scaling appears to be broken. Due to failure of Dennard scaling, (slowed supply voltage scaling) core count scaling may be in jeopardy. Researchers have projected that, at 8 nm technology nodes, the amount of Dark Silicon may reach up to 50%-80%

CISC 879 : Advanced Parallel Programming Motivation In 2024, will the processors have 32 times the performance of processors from 2008?

CISC 879 : Advanced Parallel Programming Models 3 models and their combinations are discussed: 1.Device Scaling Model 2.Single Core Scaling Model 3.Multi-core Scaling model

CISC 879 : Advanced Parallel Programming Models

CISC 879 : Advanced Parallel Programming Device Scaling Model Uses ITRS 2010 technology roadmap and conservative scaling (Borkar’s predictions) for device scaling. This provides the area, power and frequency scaling factors at future technology nodes (45nm to 8nm).

CISC 879 : Advanced Parallel Programming Device Scaling Model

CISC 879 : Advanced Parallel Programming Core Scaling Model The core-level model provides the maximum performance that a single core can sustain for any given area. Pareto-optimal frontiers for single-core area/performance and power/performance are created using a large set of processors.

CISC 879 : Advanced Parallel Programming Core Scaling Model Power/Performance frontier, 45nm Area/Performance frontier, 45nm

CISC 879 : Advanced Parallel Programming Multi-Core Scaling Model Two mainstream classes of multicore organizations, multi-core CPUs and many-thread GPUs, which represent two extreme points in the threads-per- core spectrum are modeled. To determine area, power and performance of any application for “any” chip topology for CPU like and GPU-like multicore performance.

CISC 879 : Advanced Parallel Programming Multi-Core Scaling Model Two models are presented: 1. Amdahl’s Law Upper Bounds 2. Realistic Performance Model

CISC 879 : Advanced Parallel Programming Amdahl’s law Amdahl’s law is used to find the theoretical maximum speedup using multiple processors. The law is extended to describe symmetric, asymmetric, dynamic and composed multicore topologies. The model gives the Upper Bound of parallel performance.

CISC 879 : Advanced Parallel Programming Amdahl’s law Multicore topologies: 1.Symmetric Multicore: Multiple copies of one core operating at the same voltage and frequency setting. 2. Asymmetric Multicore: One large monolithic core and many identical small cores.

CISC 879 : Advanced Parallel Programming Amdahl’s law Multicore topologies: 3. Dynamic Multicore: During parallel code portions, the large core is shut down and vice-versa. 4.Composed Multicore: A collection of small cores that can logically fuse together to compose a high-performance large core.

CISC 879 : Advanced Parallel Programming Amdahl’s law

CISC 879 : Advanced Parallel Programming Realistic Model The model discussed, does not consider the Microarchitectural features and workload behavior. This model formulates the performance of a multicore in terms of chip organization, frequency, CPI, cache hierarchy and memory bandwidth. It also includes application behavior, degree of thread level parallelism.

CISC 879 : Advanced Parallel Programming Realistic Model Model Validation

CISC 879 : Advanced Parallel Programming Model Combination 1.Device Scaling x Core Scaling Based on ITRS roadmap predictions, scaling the microarchitecture core from 45nm to 8nm will result in 3.9x performance improvement and an 88% reduction in power consumption. Based on conservative scaling, the performance will improve only 44% and 74% reduction in power consumption.

CISC 879 : Advanced Parallel Programming Model Combination 2.Device Scaling x Core Scaling x Multicore Scaling

CISC 879 : Advanced Parallel Programming Model Combination 2.Device Scaling x Core Scaling x Multicore Scaling Geometric mean of the speedup is obtained as shown in the table.

CISC 879 : Advanced Parallel Programming Summary As depicted, due to the power and parallelism limitations, a significant gap exists between what is achievable and what is expected by Moore’s Law.

CISC 879 : Advanced Parallel Programming Conclusion Amount of dark silicon increases as we scale down the technology node. Predicted speedup of 32x is not achieved by both ITRS or conservative scaling. Optimistic speedup that can be achieved is 7.9x

CISC 879 : Advanced Parallel Programming Questions?

CISC 879 : Advanced Parallel Programming Thank you