Integer Operations Computer Organization and Assembly Language: Module 5.

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Presentation transcript:

Integer Operations Computer Organization and Assembly Language: Module 5

Integer Operations u Addition  Unsigned  2’s complement, 1’s complement u Subtraction u Multiplication u Division

Unsigned Integer Addition u The algorithm for addition of unsigned integers in a positional representation works for any radix.  You learned this algorithm as a child  Given a pair of bit (digit) sequences X and Y, where X = x n x n-1...x 1 x 0 Y = y n y n-1...y 1 y 0  For i from 0 to n, add c i, x i and y i. If the sum is less than the radix assign the sum to s i and 0 to c i+1. Otherwise subtract the radix from the sum and assign the result to s i and 1 to c i+1. c i is the carry bit in the i th bit position.  Assume c 0 = 0.

Unsigned Binary Addition 011(3 10 ) +001(1 10 ) 100(4 10 ) c 0 = 0 1+1=10 c 1 =1 s0s0 Note: c i+1 =(x i +y i +c i )div 2 s i =(x i +y i +c i )mod 2

Unsigned Binary Addition

Overflow in Unsigned Addition u In a computer, the result of addition is stored in a fixed sized container: a register.  MIPS registers contain 32 bits  Sometimes the result of addition is a number too large to be represented: this is called overflow.  In unsigned addition, an overflow is indicated by a value of 1 in the most significant carry bit (often called the carry-out bit).

Overflow Example u Assume 4-bit registers Carry out of 1 from the most significant position Although the true result is 10000, the register contains 0000.

Biased Addition u The various biased representations use the same addition algorithm as unsigned integers, with one modification  The bias must be subtracted from the result

Complement Addition u The 2’s complement representation uses the same addition algorithm as unsigned integers.  The overflow condition is different  Overflow occurs if x n-1 and y n-1 both have the same value and s n-1 has a different value.  This is logically equivalent to c n-1 = c n-2  Carry-out is otherwise ignored u The 1’s complement representation adds a slight wrinkle to the addition algorithm.  If the carry-out is 1, the sum is incremented by 1.  Overflow is handled as it is for 2’s complement

2’s Complement Addition 0101 (5)0011 (3) (2) (-4) 0111 (7)1111 (-1) 0101 (5)1001 (-7) (-3) (7) (2) (0) Carry out is discarded, no overflow.

2’s Complement Addition (-8) (5) (-8) (64) (-16) (69) (126) (-126) (96) (-3) (-34) (127) overflow

0011 (+3)0001 (+1) (-3) (-6) 1111 (0)1010 (-5) 1101 (-2) 0111 (+7) (-4) (-3) (-6) 0100 (+4) 1’s Complement Addition carry-out is added to the partial sum

Integer Subtraction u The complement representations can handle subtraction as addition by first complementing the subtrahend, then adding.  There is no subtraction algorithm for complement representations. u All other integer representations require separate logic to handle subtraction.  For this reason, and because it has a unique zero, 2’s complement is used to represent integers in almost all architectures.  In such architectures, other representations are translated into 2’s complement before addition/subtraction, then the result is translated back into the original representation.

Integer Multiplication

u It may take as many as 2n bits to represent the product of two n -bit numbers. u Multiplication of unsigned binary integers can be done with the same algorithm we use for decimal multiplication. u By sign extending both the multiplier and the multiplicand to the size needed for the result, the algorithm for multiplying 2’s complement is the same as that of unsigned integers.

Multiplication Algorithm while (count < no. of integer bits){ check if the multiplier’s last bit is 1 if (multiplier bit = 1){ add the multiplicand to hi} count = count + 1 rotate the multiplier right 1 bit shift hi and lo one bit to the right }

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 0110 Multiplier Lo Using 4-bit registers, multiply 13 by 6.

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 0011 Multiplier Lo After the first shift the lo bit of the multiplier is 1, so we will add the multiplicand to hi.

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 0011 Multiplier Lo

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 1001 Multiplier Lo After the shift the low bit of the multiplier is still 1. We add the multiplicand to hi…

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 1001 Multiplier Lo …and the result is bigger than 4 bits. So carry is set to one. The carry bit is shifted into hi…

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 1100 Multiplier Lo …and the low bit of hi is shifted into lo. One more shift step will produce the answer.

Unsigned Integer Multiplication 1101 Multiplicand Hi Carry 0110 Multiplier Lo The multiplier is again The result, is 78. And 6 x 13 = 78.

u With n-bit two’s complement integers, both the multiplier and the multiplicand are sign extended to 2n. u This produces a 4n-bit result. u The correct product is contained in the least significant 2n bits of the 4n-bit result. 2’s Complement Multiplication

2’s complement Multiplication 1101 Multiplicand Hi Carry 0110 Multiplier Lo Interpreted as 2’s complement numbers, this result is –3 x 6 = 78, which is obviously false.

2’s complement Multiplication Multiplicand Hi Carry Multiplier Lo For an accurate result we must sign extend the multiplier and multiplicand to 8 bits.

2’s complement Multiplication Multiplicand Hi Carry Multiplier Lo After multiplication, lo contains all the meaningful data: = - 18, which is –3 x 6!

Division u Division of unsigned binary integers is the performed similar to the longhand division of decimal numbers u No convenient algorithm exists for division of signed magnitude and complement integers  Determine sign of the result  Take absolute value of the numbers  Do unsigned division  Convert the result to the original format

Division Algorithm remainder = dividend while count < no. of integer bits + 1{ remainder = remainder - divisor if (remainder < 0){ remainder = remainder + divisor shift left quotient & set lsb to 0 else shift left quotient & set lsb to 1 } shift the divisor right count = count + 1 }