An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.

Slides:



Advertisements
Similar presentations
Bart Jansen 1.  Problem definition  Instance: Connected graph G, positive integer k  Question: Is there a spanning tree for G with at least k leaves?
Advertisements

An Introduction to Channel Routing
Introduction to Algorithms Rabie A. Ramadan rabieramadan.org 2 Some of the sides are exported from different sources.
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology Szu-Yu Chen, Yao-Wen Chang ICCAD 2010.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
5-1 Chapter 5 Tree Searching Strategies. 5-2 Satisfiability problem Tree representation of 8 assignments. If there are n variables x 1, x 2, …,x n, then.
S. J. Shyu Chap. 1 Introduction 1 The Design and Analysis of Algorithms Chapter 1 Introduction S. J. Shyu.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Rajat K. Pal. Chapter 3 Emran Chowdhury # P Presented by.
Chapter 3 The Greedy Method 3.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 11 - Combinational.
Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm Sadiq M. Sait, Mustafa I. Ali, Ali Zaidi.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
3 -1 Chapter 3 The Greedy Method 3 -2 The greedy method Suppose that a problem can be solved by a sequence of decisions. The greedy method has that each.
Implicit Hitting Set Problems Richard M. Karp Harvard University August 29, 2011.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 21: April 15, 2009 Routing 1.
VLSI Routing. Routing Problem  Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect.
A General Framework for Track Assignment in Multilayer Channel Routing (Multi layer routing) -VLSI Layout Algorithm KAZY NOOR –E- ALAM SIDDIQUEE
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 19: April 9, 2008 Routing 1.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Chapter 5: Computational Complexity of Area Minimization in Multi-Layer Channel Routing and an Efficient Algorithm Presented by Md. Raqibul Hasan Std No.
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
General Routing Overview and Channel Routing
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Toshihide IBARAKI Mikio KUBO Tomoyasu MASUDA Takeaki UNO Mutsunori YAGIURA Effective Local Search Algorithms for the Vehicle Routing Problem with General.
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
9/4/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (I)
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
© The McGraw-Hill Companies, Inc., Chapter 3 The Greedy Method.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
Global Routing.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
Network Aware Resource Allocation in Distributed Clouds.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-Path Steiner Graph Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, and Shih-Hung Weng UC San.
Chapter 12 Recursion, Complexity, and Searching and Sorting
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
Efficient Multi-Layer Obstacle- Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu,Meng-Xiang Li, Yao-Wen Chang.
A Study of Balanced Search Trees: Brainstorming a New Balanced Search Tree Anthony Kim, 2005 Computer Systems Research.
GLOBAL ROUTING Anita Antony PR11EC1011. Approaches for Global Routing Sequential Approach: – Route the nets one at a time. Concurrent Approach: – Consider.
Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.
ECE 260B – CSE 241A /UCB EECS Kahng/Keutzer/Newton Physical Design Flow Read Netlist Initial Placement Placement Improvement Cost Estimation Routing.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 13: March 3, 2015 Routing 1.
Detailed Routing مرتضي صاحب الزماني.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
Implicit Hitting Set Problems Richard M. Karp Erick Moreno Centeno DIMACS 20 th Anniversary.
R-Trees: A Dynamic Index Structure For Spatial Searching Antonin Guttman.
Efficient Resource Allocation for Wireless Multicast De-Nian Yang, Member, IEEE Ming-Syan Chen, Fellow, IEEE IEEE Transactions on Mobile Computing, April.
مرتضي صاحب الزماني 1 Detailed Routing. مرتضي صاحب الزماني 2 Greedy Routing “ A greedy channel router ”, Rivest, Fiduccia, Proceedings of the nineteenth.
Chapter 13 Backtracking Introduction The 3-coloring problem
2/27/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (II)
EE4271 VLSI Design VLSI Channel Routing.
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1.
VLSI Physical Design Automation
VLSI Physical Design Automation
ESE535: Electronic Design Automation
Optimal Non-Manhattan Bubble Sort Channel Router
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
Detailed Routing مرتضي صاحب الزماني.
VLSI Physical Design Automation
Fast Min-Register Retiming Through Binary Max-Flow
ICS 252 Introduction to Computer Design
Presentation transcript:

An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt

Motivation: routing for automated leaf cell generation  1-D and 1.5-D cells  channel routing seems more adequate than maze routing  Scenario somewhat different from conventional inter cell channel routing

Motivation: channel routing for automated leaf cell generation  a typical routing channel in a standard cell layout looks like this:  long channel with many tracks

Motivation: channel routing for automated leaf cell generation  a typical routing channel in a standard cell layout looks like this:  long channel with many tracks  fast algorithms like “Greedy Router” perform very well: they need only one or two tracks more than the optimal solution

Motivation: channel routing for automated leaf cell generation  a typical routing channel in a standard cell layout looks like this:  long channel with many tracks  fast algorithms like “Greedy Router” perform very well: they need only one or two tracks more than the optimal solution  some algorithms need a few extra columns

Motivation: channel routing for automated leaf cell generation  a channel in a leaf cell is much smaller

Motivation: channel routing for automated leaf cell generation  a channel in a leaf cell is much smaller  the use of extra area is relatively expensive

Motivation: channel routing for automated leaf cell generation  a channel in a leaf cell is much smaller  the use of extra area is expensive  or might simply be not feasible

Motivation channel routing for automated leaf cell generation small problem instances:  small constant area overhead of heuristical algorithms becomes a large relative area overhead  asymptotically slow algorithms can be practical  difficult instances  obstacles / keep-out regions  dense terminal placement

Problem Formulation routing model  grid-based  all elements are aligned to a routing grid  over-the-cell-routing  terminals can be located anywhere in the channel, not only at the top or bottom boundary  restricted two layer model  one layer for horizontal connections (trunks)  one layer for vertical connections (doglegs)  arbitrary obstacles  Each signal crosses each column at most once  (no forks or detours) Grid-based over the cell channel routing in the restricted two layer routing model

Problem Formulation example channel segment  Connect all terminals that belong to the same net in a channel of length n and a given height of t tracks

Problem Formulation example channel segment  Connect all terminals that belong to the same net in a channel of length n and a given height of t tracks

Algorithmic Approach decision problem  algorithm does not search for a minimum height routing  tries to find a routing for a given channel height of t tracks  this is all that is needed for constant height leaf cells  minimization is done by iterating over t  obviously increases the runtime  in the paper we show that the overhead is only O(1)

Algorithmic Approach dynamic programming  Sweep over the channel from left to right column by column like the “Greedy Router”  Use track assignments to record for each track the signal that leaves the current column on this track  “Greedy Router” heuristically selects one track assignment for each column  We enumerate all reachable track assignments for the column  Dynamic programming prevents an exponential growth of the search space with the channel length

Algorithm pseudo code for (each column) { for (each possible track assignment m of the previous column) {  check if m valid in this column with respect to terminals and obstacles; use m to generate new track assignments by adding all combinations of doglegs; }

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

1 1 Algorithm example  Denote a track assignment by a t-tupel of integers in the range [0,..., t], where 0 means an empty track  How can can signals 1 and 2 leave column 5 and enter column 6?

Algorithm details of column processing // takes as input a set M i-1 of all track assignments of column i-1 and // produces a set M i of all track assignments for column i next_column(M i-1, i) { M i := Ø; for (each m  M i-1 ) { m := removeRightEdgeTerminals(m, i-1); m := addLeftEdgeTerminals(m, i); m := connectTerminals(m, i); m := checkForObstacles(m, i); if (m ≠ 0) { M i := M i  {m}; M i := M i  doglegs(m); }

removeRightEdgeTerminals() addLeftEdgeTerminals()  Remove all signals that had their last terminal on the previous column.  Add signals to the assignment that have their first terminal on the current column.  Delete assignment if above is impossible

removeRightEdgeTerminals() addLeftEdgeTerminals()  Remove all signals that had their last terminal on the previous column.  Add signals to the assignment that have their first terminal on the current column.  Delete assignment if above is impossible

removeRightEdgeTerminals() addLeftEdgeTerminals()  Remove all signals that had their last terminal on the previous column.  Add signals to the assignment that have their first terminal on the current column.  Delete assignment if above is impossible

connectTerminals()  Existing signals might have terminals in this column that are not connected by the incoming assignment.  Add dogleg to connect the signal to the terminal.  Delete the assignment if the track with the terminal is blocked by another signal

doglegs()  Enumerate all the possible dogleg combinations for this assignment.  Multiple layouts might generate the same track assignment.  These layouts are equivalent under routability aspects  only one is selected by dynamic programming  selection can be used to minimize number of vias, wire length,

Computational Complexity worst case  Up to t! possible assignments per column  dogleg() dominates all other subroutines  less than 2 t/2 doglegs per assignment  worst case runtime per column O(t!2 t )  O(nt!2 t ) for a channel of length n  fixed parameter tractable:  overall runtime linear for a fixed channel height  runtime exponential in the channel height

Data Structures MDDs  Represent the set of track assignments by its characteristic function f:[0,..., t] t  {0, 1}  represent f by an MDD (Multi Valued Decision Diagram)  reduces the size of the representation  typically 1M assignments require 80K MDD-nodes  allows efficient manipulation of the assignments in the set

Data Structures MDD example  MDD representation of the example set in column 6  connections to the 0-terminal are omitted for clarity Track 0 Track 1 Track 2 Track

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example Track 0 Track 1 Track 2 Track  Each path from the root to the 1-terminal represents a track assignment

Data Structures MDD example: LeftEdgePorts()  To be able to connect a new signal to track 2 the subset of assignments with an empty track 2 must be found  calculate cofactor f| track2=0 4 1 Track 0 Track 1 Track 2 Track

Data Structures MDD example: LeftEdgePorts()  To be able to connect a new signal to track 2 the subset of assignments with an empty track 2 must be found  calculate cofactor f| track2=0 4 1 Track 0 Track 1 Track 2 Track

Data Structures MDD example: LeftEdgePorts()  To be able to connect a new signal to track 2 the subset of assignments with an empty track 2 must be found  calculate cofactor f| track2=0 4 1 Track 0 Track 1 Track 2 Track

Data Structures MDD example: LeftEdgePorts()  To insert signal 4 in the empty track move track 2 edges from 0 to Track 0 Track 1 Track 2 Track

Data Structures MDD example: LeftEdgePorts()  To insert signal 4 in the empty track move track 2 edges from 0 to Track 0 Track 1 Track 2 Track

Data Structures MDD example: LeftEdgePorts()  To insert signal 4 in the empty track move track 2 edges from 0 to Track 0 Track 1 Track 2 Track

Experimental results runtime per column in milliseconds #tracksHashset MDD

Conclusion  Intra cell channel routing can be solved exactly by exhaustive enumeration of reachable track assignments  dynamic programming yields a runtime linear in the channel length  Possible application to conventional channel routing:  less than exhaustive search  more than one assignment per column as “Greedy Router” does.  => heuristically select a set of maybe a few hundred track assignments for each column