doc.: CNTR SubmissionSlide 1 26/02/2016 Slide 1 Simulation result for Preliminary PHY proposal and alternative proposed set of Guard Chip Notice: This document has been prepared to assist IEEE DYSPAN SC. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE DYSPAN SC. Patent Policy and Procedures: The contributor is familiar with the IEEE Patent Policy and Procedures, including the statement "IEEE standards may include the known use of patent(s), including patent applications, provided the IEEE receives assurance from the patent holder or applicant with respect to patents essential for compliance with both mandatory and optional portions of the standard." Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chair as early as possible, in written or electronic form, if patented technology (or technology under patent application) might be incorporated into a draft standard being developed within IEEE DYSPAN SC. If you have questions, contact the IEEE Patent Committee Administrator at. Date: Authors:

doc.: CNTR SubmissionSlide 2 Abstract  This contribution presents the revised simulation results supported for the Preliminary PHY Proposal for IEEE System (doc.: CNTR )  Also it presents a revised method to determine the optimum values of guard chip for multi-code DSSS based PHY design. 26/02/2016 Slide 2

doc.: CNTR Submission PHY Design (1/2) 26/02/2016 Slide 3 ItemsSpec 1Spec 2 Modulation SchemeQPSK Symbol Rate50ksps25 ksps Data Rate100 kbps50 kbps Number of Sequence3163 Sequence5- stage M-Sequence6 Stage M-Sequence Guard chip59 Length of extended sequence3672 Chip rate1.8 MHz Cyclic shift interval59 Number of cyclic shifted code67 Number of pilot channel11 Number of data channel56 Max transmission rate500 kbps300 kbps

doc.: CNTR Submission PHY Design (2/2) 26/02/2016 Slide 4 ItemsSpec 3Spec 4 Modulation SchemeQPSK Symbol Rate50ksps25 ksps Data Rate100 kbps50 kbps Number of Sequence3163 Sequence5- stage M-Sequence6 Stage M-Sequence Guard chip59 Length of extended sequence3672 Chip rate1.8 MHz Cyclic shift interval11 Number of cyclic shifted code3163 Number of pilot channel11 Number of data channneel3062 Max transmission rate3 Mbps3.1 Mbps

doc.: CNTR Submission Outdoor Channel Model Table 1 shows the calculated RMS Delay Spread based on VHF band measurement results for Japan Public broadband network [1].The average RMS delay spread highly depends on the environment such as terrain type. [1] M. OODO, N. SOMA, R. FUNADA and H. HARADA, “Channel Model for Broadband Wireless Communication in the VHF-band”, IEICE Technical Report Index of Measured Points P16P5P4P1P3P6P15P2P7P14P8P13P12P11P10P9 Distance (km) RMS Delay Spread (µs) Measure frequency 200MHz H b =45m H m =2m BS Power 20W Slide 5

doc.: CNTR Submission Indoor channel Model 26/02/2016 Slide 6 [2] Theodore S. Rappaport, Wireless Communications: Principles and Practice (2nd Edition), Prentice Hall, ISBN: Publish Date: Dec 31, 2007 [2]

doc.: CNTR Submission Delay Spread used in the simulation Indoor delay spread< 270 ns (2.7e-7) Outdoor delay spread< 0.5 us (5 e-7) 26/02/2016 Slide 7

doc.: CNTR Submission 26/02/2016 Slide 8 54 MHz806 MHz Fd=400 Hz7992 km/hr536 km/hr Fd=100 Hz1998 km/hr134 km/hr Fd=40 Hz799.2 km/hr53.6 km/hr Speed of airplane: 885 km/hr Speed of bullet train: 300 km/hr Performance for 2 path Rayleigh Fading

doc.: CNTR Submission DETERMINATION OF OPTIMUM GUARD CHIP 26/02/2016 Slide 9

doc.: CNTR Submission Guard chips calculation (Spec 3) 26/02/2016 Slide 10 ModulationQPSK16 QAM64 QAMUnit Chip Rate1.8 Mcps Guard Chipxxxchips Length of chips per symbol31 + x chips Cyclic shift interval111chips Symbol Rate1.8/(31+x) Msps Max transmission data rate1.8 *30*2/(31+x)1.8*30*4/(31+x)1.8*30*8/(31+x)Mbps Expected data rate for M2M10 Mbps X chips Transmission data rate Mbps

doc.: CNTR Submission Data throughput vs. different number of guard chips (Spec 3) 26/02/2016 Slide 11 Guard chip (bits) SNR=20, error (mbps) SNR=25, error (mbps) SNR=30, error (mbps) These table and chart are based on QPSK modulation scheme. From simulations and calculations, larger number of guard chips obtained fewer number of error shown in the table. However, due to the larger overhead incurred, the effective data throughput is reduced as the the number of guard chip increases as shown on the left.

doc.: CNTR Submission Summary  From the above simulations and calculations, we find that larger number of guard chip though obtain few number of the error, the effective data throughput is reduced as more overhead bits are involved.  Hence, I would like to revised that guard chip 5 and guard chip 9 are better for spec 3 and 4. 26/02/2016 Slide 12

doc.: CNTR Submission Conclusion  In this presentation, a revised simulation results are presented, as well as a revised method of determining the optimum number of guard chip.  From the calculations and simulations, we would like to propose to have 5 guardchips for spec 3 and 9 guardchips for spec 4. 26/02/2016 Slide 13

doc.: CNTR Submission Appendix 26/02/2016 Slide 14 ModulationQPSK16 QAM64 QAMUnit Chip Rate1.8 Mcps Guard Chipxxxchips Length of chips per symbol63 + x chips Cyclic shift interval111chips Symbol Rate1.8/(63+x) Msps Max transmission data rate1.8 *62*2/(63+x)1.8*62*4/(63+x)1.8*62*8/(63+x)Mbps Expected data rate for M2M10 Mbps X chips Transmission data rate Mbps Guard chips calculation (Spec 4)