11 Pipelining Kosarev Nikolay MIPT Oct, 2009

22 Pipelining Implementation technique whereby multiple instructions are overlapped in execution Each pipeline step (stage) completes a part of instruction Time to move instruction one step is processor cycle. Cycle length – time required for the slowest pipe stage Pipelining yields a reduction in the average execution time per instruction –Time per instruction = time per instruction on unpipelined machine / number of pipe stages –CPI (clocks per instruction) = 1/IPC (instructions per cycle)

33 Simple RISC pipeline InstructionClock number number i IFIDEXMEMWB i+1 IFIDEXMEMWB i+2 IFIDEXMEMWB

44 Basic pipe stages 5 basic pipe stages for each instruction Instruction fetch (IF) –Send PC to memory and fetch the current instruction. Update PC. Decode / register fetch (ID) –Decode instruction and / then read registers for source operands from RF (register file). Check branch, compute branch target address. Execution / effective address (EX) –ALU operates to calculate effective address / perform operation Memory access (MEM) –Access memory using effective address Write-back (WB) –Write result from memory or ALU to RF

55 General restrictions Ensure that different instructions don’t interfere with one another (pipeline registers used) Don’t perform two different instructions with the same data path on the same cycle

66 Pipeline hazards Prevent the next instruction from executing in its designated clock cycle Reduce performance from its ideal speedup gain by pipelining 3 types of hazards –Structural – arise from resource conflicts –Data – an instruction depends on the results of the previous instruction due to overlapping in the pipeline –Control – arise from instructions that change the PC Hazards may cause pipeline stalls (or bubbles) Speedup = Pipeline depth / (1+pipeline stall cycles per instruction)

77 Structural hazards Arise due to resource conflicts Common cases –Functional units is not fully pipelined (e.g. divider) –Resource is not duplicated enough (e.g. RF ports) Why designer allows them? –The reason is cost

88 Data hazards Due to change in the order of read/write accesses to operands (in cmp with unpipelined) Conflict could be minimized by bypassing (forwarding) –ADD r1 = r2, r3 –SUB r4 = r1, r5 –AND r6 = r1, r7 –XOR r8 = r1, r9 Stall otherwise (by pipeline interlock logic) –LD r1 = r2, (r3) –SUB r4 = r1, r5 –AND r6 = r1, r7 –XOR r8 = r1, r9

99 Control hazards Arise from instructions that change PC Taken / not taken branches Methods to deal with branches –Stall the pipeline –Treat as not-taken –Delayed branch –Branch instruction –Sequential successor (in branch delay slot) –Branch target if taken –Cancelling branch Speedup = Pipeline depth / (1+branch frequency * branch penalty)