C code organization CSE 2451 Rong Shi

Topics C code organization Linking Header files Makefiles

#include #include works with two types of files – Library files #include – Local files #include “filename” #include “directory/subdirectory/filename” By convention, the names of the standard library header files end with a.h suffix Location of library files – /usr/include

C code organization

Working with multiple files

Compiling The -c option on the gcc command compiles to object code Then gcc with -o option merges object files into one executable file Note that “makefunction.h” is only referred to in a #include statement, never in a compilation command

Another example – circular #includes main.c #include “a.h” #include “b.h” void main() { a(10); } a.h #include #include “b.h” void a(int num) { if(num != 0) { num = b(num-1); printf(“%i”, num-1); } b.h #include #include “a.h” int b(int num) { if(num != 0) { num = a(num/2); printf(“%i”, num); return num; } return 0; }

Conditional inclusion #ifndef HEADER_FILE_NAME_H_ #define HEADER_FILE_NAME_H_ // contents of header_file_name.h goes here // … #endif

Makefile overview Makefiles are a commonly used tool to handle compilation of large software projects in UNIX Makefiles contain UNIX commands and will run them in a specified sequence Mandatory makefile file names: makefile or Makefile You can only have one makefile per directory Anything that can be entered at the UNIX command prompt can be in the makefile Each command must be preceded by a TAB and is immediately followed by a carriage return To execute, be in the directory where the makefile is: – % make tag-name (also called section name) – examples: make make all make clean

Makefile example # this line is a comment all: mainprog mainprog: makefunction.o mainprog.o gcc makefunction.o mainprog.o -o mainprog makefunction.o: makefunction.c gcc -c makefunction.c mainprog.o: mainprog.c gcc -c mainprog.c clean: rm -rf *.o mainprog

Makefile details We could compile our example like this: – gcc -o mainprog mainprog.c makefunction.c But what if we made changes to only makefunction.c? A makefile is often composed of lines with the following format: – target: dependencies [tab] system command – The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. – make with no arguments executes the first rule in the file.

Makefile dependencies Useful to use different targets – Because if you modify a single project, you don’t have to recompile everything, only what you modified In the example makefile: – All has only dependencies, no system commands – For make to execute correctly, it has to meet all the dependencies of the called target – Each of the dependencies are searched through all the targets available and executed if found. – make clean Get rid of all the object and executable files – Free disk space – Force recompilation of files

Additional information on makefiles make.html make.html Variables in makefiles