Tracking Millions of Flows In High Speed Networks for Application Identification Tian Pan, Xiaoyu Guo, Chenhui Zhang, Junchen Jiang, Hao Wu and Bin Liut Tsinghua National Laboratory for Information Science and Technology Department of Computer Science and Technology, Tsinghua University, Beijing 10084, China 2012 Proceedings IEEE INFOCOM 1 通訊所 周啓松

Outline Framework of system External flow table management ALFE replacement policy Theoretical analysis Evaluation Conclusion 2

FRAMEWORK OF SYSTEM 3

Emerge issues On-chip SRAM is fast but insufficient to accommodate millions of concurrent flows which has to be stored in DDR or RLDRAM. High hash collision rate and high cache miss rate. It is hard to attach parallel off-chip DRAMs to gain performance improvement. 4

Purpose An on-chip/off-chip hierarchical flow table to achieve high speed packet lookup and maintain tens of millions of flows. Adaptive Least Frequently Evicted(ALFE), which keeps the elephant flows longer in the cache thus increasing the cache hit rate. An efficient management scheme is proposed to exploit DRAM's burst feature. Real trace evaluation on Altera FPGA platform indicates, with 200MHz internal clock, small sized cache with 16K entries can achieve up to 80% hit rate, enabling more than 70Mpps line rate flow tracking even at the 40-byte packets. 5

Framework of the Proposed Application Identification 6

Design Trade-offs and System-level Optimization Stateless TCP Handling without Flow Reconstruction ◦ 3-Way shaking ◦ FIN/RST Fixed-allocated Hash Buckets to Exploit DRAM Bursts ◦ Lower utilization of memory space Cache Replacement Policy to Track Elephant Flows ◦ Heavy-tailed distribution lmpact of Misidentification 7

EXTERNAL FLOW TABLE MANAGEMENT 8

Flow Record Data Structure 9

Fixed-allocated Hash Bucket How to store the flow records How to read/write the memory efficiently 10

Device Independent Layer 11

Memory Swapping Logic 12

ALFE REPLACEMENT POLICY 13

Heavy-tailedness 14

Replacement Policy 15

THEORETICAL ANALYSIS 16

Poisson Queuing Network System 17

Throughput and Queue Length 18

EVALUATION 19

Experiment Setup 20

On-chip Flow Cache 21

Off-chip Flow Table 22

Bucket Overflow 23 NE BAW

Memory Utilization 24

Delay and Throughput The 400MHz DRAM I/O interface transfers two data words per DRAM clock cycle. The read latency is 6 DCs. The write latency is 7 DCs. The maximum throughput of DRAM is 44.44Mpps. 25

Trade-off between Utilization and Speed 26

Power 27

System Overall Performance System Throughput ◦ Overall throughput under different cache entry number 28

29 avalanche effect

Conclusion Detail of Matching Engine should be listed. Setup time of flow table should be taken into account System Overall Performance. 30