Fixing GND in IBIS Walter Katz SiSoft IBIS-Packaging May 6 2015.

Slides:



Advertisements
Similar presentations
How to Build Macro-Models in Tina SPICE
Advertisements

ECE 3130 – Digital Electronics and Design
Package Die Ports Walter Katz IBIS Interconnect 10/31/12.
Sweeping a Variable Resistor Wheatstone Bridge. Place the Parts 1.VDC 2.R, which you place 3 times. The numbering of the resistor increases sequentially.
Package EBD/EMD Walter Katz IBIS Interconnect 11/13/12.
Package and On-Die Interconnect Decisions Made and Proposed Solutions Walter Katz IBIS ATM December 3, 2013.
Interconnect Terminal Naming Walter Katz Signal Integrity Software, Inc. IBIS ATM January 9, 2015.
Terminal Draft 2 Walter Katz Signal Integrity Software, Inc. IBIS Interconnect July 9, 2014.
IBIS-ISS Package Status Walter Katz IBIS ATM December 17, 2014.
IBIS Interconnect Decision Time Walter Katz IBIS Interconnect 6/19/13.
EMC of ICs Practical Trainings. 2 May 15 Objectives Get familiar with IC-EMC/Winspice Illustrate parasitic emission mechanisms Understand parasitic emission.
Experiments 8 and 9. Same Circuit: Experiment 8 and 9 You should use the +5 V and +9 V supplies on the ANDY board. You should use red wire to bring the.
Field Effect Transistors Circuit Analysis EE314 HP PA8000 Fujitsu Fairchild Clipper C100.
Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure.
Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure.
CMOS Invertors Lecture #3. Step 1: Select Foundary.
An Inverting Amplifier. Op Amp Equivalent Circuit The differential voltage v d = v 2 – v 1 A is the open-loop voltage gain v2v2 v1v1 An op amp can be.
IBIS Interconnect BIRD Draft 3 Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon Santa Clara, CA January 30, 2015.
01/30/04 *Other brands and names are the property of their respective owners Page 1 Futures Subcommittee Proposed “New” Futures Subcommittee To create,
Signal Integrity Software, Inc.Electronic Module Description© SiSoft, 2008 Electrical Module Description EMD A new approach to describing packages and.
Interconnect Modeling Status Draft 1 Walter Katz … IBIS Summit, DesignCon January 31, 2013.
Behavioral Buffer Modeling with HSPICE – Intel Buffer
IBIS-ISS Package Proposal Status Walter Katz IBIS ATM January 7, 2014.
© 2007 Cisco Systems, Inc. All rights reserved. 1 IBIS Quality Review A status review of the IBIS Quality specification Mike LaBonte, Cisco Systems.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Updated Interconnect.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 5: Layout.
First, let’s review the structure and use of a breadboard.
03/05/04 *Other brands and names are the property of their respective owners Intel Confidential Page 1 Original Cookbook Objectives Triage to find keywords.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 3: Layout.
Last week’s project demos RC circuit with creative use of 7- segment display Demo in class tonight – don’t start on the next project until I’ve seen this.
16- Agenda S-Parameters and Linear Analysis 4 Transmission Lines and Field Solver 5 IBIS 6 DAY 2 Synopsys 60-I-032-BSG-005 © 2007 Synopsys, Inc. All Rights.
Package Modeling Status Walter Katz IBIS Open Forum December 6, 2013.
12/4/2002 The Ground Conundrum - Class 20 Assignment: Find and research papers on this subject, be prepared to defend research.
Backchannel Issues Walter Katz Signal Integrity Software, Inc. IBIS-ATM April 8, 2014.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs Draft Presented September 23, 2015 at the Interconnect Working Group Copyright.
Intel Confidential IBIS & ICM Interfacing: A New Proposal Michael Mirmak Signal Integrity Engineering Intel Corp. Chair,
A Tour of the IBIS Quality Specification DesignCon East IBIS Summit April 5, 2004 Robert Haller Signal Integrity Software, Inc. 6 Clock.
06/02/04 *Other brands and names are the property of their respective owners Page 1 New IBIS Cookbook 1.0 Introduction.
ECE 2372 Modern Digital System Design Section 4.8 Xilinx Schematic Capture Simulation Tutorial.
Signal Integrity Software, Inc.Electronic Module Description© SiSoft, 2008 Electrical Module Description EMD A new approach to describing packages and.
Field Effect Transistors (2)
EMD Overview Walter Katz IBIS Open Forum March 15, 2013.
10/07/04 *Other brands and names are the property of their respective owners Page 1 IBIS & ICM Interfacing Options Alternative.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Updated Interconnect.
Pin Mapping Key Concepts From IBIS 6.0… “The [Pin Mapping] keyword names the connections between POWER and/or GND pins and buffer and/or terminator voltage.
Interconnect Terminal Mapping Figures 30 Sep
I/O Buffer Modeling Class 10 2 lectures
Fixing [Pin Mapping] Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon Santa Clara, CA January 22, 2016.
References in IBIS Bob Ross, Teraspeed Labs IBIS ATM Meeting January 12, 2016 Copyright 2016 Teraspeed Labs 1.
Simulation [Model]s in IBIS Bob Ross, Teraspeed Labs Future Editorial Meeting April 22, 2016 Copyright 2016 Teraspeed Labs 1.
[Die Supply Pads] Walter Katz Signal Integrity Software, Inc. IBIS Interconnect January 6, 2016.
IBIS Interconnect BIRD Draft 0 Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon January 27, 2015.
[Pulldown Reference] [GND Clamp Reference] Offset in [Pulldown] [Ground Clamp] Walter Katz IBIS GND Editorial March 4, 2016.
MICROPROCESSOR DESIGN1 IR/Inductive Drop Introduction One component of every chip is the network of wires used to distribute power from the input power.
Piero Belforte, HDT 1998: Advanced Simulation and Modeling for Electronic System Hardware Design Part2 .
IBIS 6.2 Editorial Resolutions
BIRD Terminology Issues Bob Ross
A tutorial guide to start with ISE
Walter Katz IBIS-ATM December 8, 2015
IBIS Interconnect Task Group December 15, 2015
Chapter 6b Co-simulation of chip, package and board
Chapter F – Mux / demux.
DUT vs DIA Device Under Test vs Device In Action
New IBIS Cookbook 1.0 Introduction 2.0 Pre-Modeling Steps
Chapter 7 Co-simulation of chip, package and board
Pin Reference Concerns Bob Ross, Teraspeed Labs
Ground Recommendations Review of Recent Discussion
Init should return just equalization of buffer
IBIS 6.2 Editorial Resolutions
IBIS Interconnect Task Group August 23, 2017
Presentation transcript:

Fixing GND in IBIS Walter Katz SiSoft IBIS-Packaging May

The Power Aware Schematic

What are Currents and Voltages when Tx is in High State? “Current” at Tx is same as current at Rx “Current” at Tx is function of (Tx-VDD_Tx) and Pullup IV “Current” at Rx is function of (Rx-VDD_Rx) and Power Clamp (Rx-Tx) is function of “Current” and values of R1, R2, R3. VDD_Rx, VSS_Rx, VDD_Tx, VSS_Tx can all be calculated relative to VSS_VRM and are a function of VDD_VRM, R4:11 and currents consumed by all of buffers in Rx chip and all of the buffers in Tx chip.

What are Currents and Voltages when Tx is in Low State? “Current” at Tx is same as current at Rx. “Current” at Tx is function of (Tx-VSS_Tx) and Pulldown IV. “Current” at Rx is function of (Rx-Vss_Rx) and Ground Clamp. (Rx-Tx) is function of “Current” and values of R1, R2, R3. VDD_Rx, VSS_Rx, VDD_Tx, VSS_Tx can all be calculated relative to VSS_VRM and are a function of VDD_VRM, R4:11 and currents consumed by all of buffers in Rx chip and all of the buffers in Tx chip.

Global Ground and IBIS Reference Voltages? There is no Global Ground node in this schematic. All references in IBIS that refer to GND or Global Ground need to be changed to say that these GND nodes refer to the buffer local ground rail. What is the meaning of a non-zero value of the Pulldown or Ground Clamp Reference in an IBIS file? This is the voltage applied to the buffer local ground (relative to the test fixture local ground) that was used to measure the IV curves The current generated by the IV curve in simulation is the voltage between A_signal and the voltage at the pulldown (or GND clamp).

Does are New Packaging Scheme Support this View? Mostly, as long as the interconnect models do not contain Global Ground. The Terminator Model is not fully supported in the new package scheme If the interconnect models contain Global Ground, the accuracy of simulations will be limited by the accuracy of the voltages at VSS_Tx and VSS_Rx since not all currents to nodes between VSS_Tx and VSS_Rx will be accounted for.

The Terminator Model

Alternative Terminator Model Replace C_comp with C_comp_power_clamp and C_comp_gnd_clamp Replace symbol with “Local_GND” Replace R-pkg, L_pkg, and C_pkg with new package model IBIS-ISS subckt with terminals: A_signal A_pcref A_gcref A_locref (New local reference node) Pin_A_signal Pin_signal_name (e.g. VDD connected to A_pcref) Pin_signal_name (e.g. VEE connected to A_gcref) Pin_signal_name (e.g. VSS connected to A_locref)

Change to [Buffer Rail Mapping] Add new column local_gnd [Buffer Rail Mapping] columns: Pin_name pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref local_gnd

IBIS “GND” Changes in [Model]s The ground symbol and name “GND” within buffer models shall refer to a local ground. The signal name of this local ground must be a signal name that exists in the [Component] [Pin] section, and associated with the gnd_clamp_ref, pulldown_ref or local_gnd_ref in the [Buffer Rail Mapping] record for the Pin associated with the buffer instance. If a buffer has unique signal names gnd_clamp_ref, pulldown_ref or local_gnd_ref then pulldown_ref.

IBIS “GND” Changes in Legacy Package Models Power aware simulations with legacy package models will not correctly account for all currents to ground. IBIS 7.0 should simply state this and recommend that the new IBIS-ISS package modeling be used to correctly account for these currents.