Nanometer Technology © Copyright 2002, Fairview Ridge Partners, LLC All Rights Reserved Nanometer Technology AKI Expert Session

Nanometer Technology Agenda IC Primer IC Economics Fabrication Trends Design Trends Testing Trends Q&A

Nanometer Technology Moore’s Law IC fabrication technology has reduced the size of the average electrical component by 100,000 times in about 35 years! Fundamental physical limits are within sight. 1 (meter) (nanometer) (micron) (millimeter) H nucleus 1x polio virus 30x10 -9 semiconductors 0.13x10 -6 human hair 0.1x10 -3 Nanometer semiconductors 90x10 -9 First transistors 0.1x10 -3

Nanometer Technology Light Light is a form of electromagnetic radiation (EMR) EMR is categorized by wavelength Natural light is “in-coherent” (includes many wavelengths) Laser light is coherent (only one wavelength) 1 (meter) (nanometer) (micron) (millimeter) radiomicrowaveinfraredUVX-rays 3 MHz 3 THz3 GHz Frequency (Hertz) = wavelength/speed of light

Nanometer Technology Light Light is a form of electromagnetic radiation (EMR) EMR is categorized by wavelength Natural light is “in-coherent” (includes many wavelengths) Laser light is coherent (only one wavelength) 1 (meter) (nanometer) (micron) (millimeter) radiomicrowaveinfraredUVX-rays 3 MHz 3 THz3 GHz 1 (meter) (nanometer) (micron) (millimeter) H nucleus 1x polio virus 30x10 -9 semiconductors 0.13x10 -6 human hair 0.1x10 -3 Nanometer semiconductors 90x10 -9 First transistors 0.1x10 -3

Nanometer Technology Semiconductor Materials A semiconductor is a –crystalline substance (silicon, germanium, etc.) that conducts electricity better than an insulator (glass) but not as well as a true conductor (metal). A transistor is an –electronic device containing a semiconductor and having at least three electrical contacts, used in a circuit as an amplifier, detector, or switch An integrate circuit (IC) is a –microelectronic semiconductor device consisting of many interconnected transistors and other components Integrated circuits can be classified into analogue, digital or hybrid

Nanometer Technology

Making IC Starting with a substrate (usually Silicon) Using photolithography, circuit patterns are laid down layer-by-layer. Different areas of the substrate are doped with other elements to make them either p-type or n-type Grown insulators isolate different electrical regions Conductors tracks are etched in layers deposited over the surface. substrate N-type P-type insulator conductor

Nanometer Technology Microelectronic Economics Growth and innovation is fueled by falling prices –Both require huge capital expenditures Continuously reducing costs through improving production efficiency is critical to profits Chip cost is comprised of many factors –Design costs including: CPU time EDA tools cost Validation testing (+ Design for Testability overhead) –Fabrication cost –Production testing cost Both wafer and chip level

Nanometer Technology Simple Cost Analysis Example: new IC intended to sell for $20 with an expected production volume of one million (1M) Cost components: –Design CPU time — $20K –Design EDA tools — $100K –Validation test cost — $250K –Fabrication cost — $20M –20 sec production test cost $0.10/sec)— $2M

Nanometer Technology Fabrication Obstacles Feature size is approaching the wavelength of the light used to “print” the circuit elements. –Costly deep-UV and X-ray lithography techniques will be required to take the next density step High margin growth products require costly new (I.e. mixed signal) processing capability Improving production efficiencies (“yields”) requires “shrinking” designs and/or increasing wafer size

Nanometer Technology “Printing” IC As the dimensions of the components approach the wavelengths of the imaging source, making reproducible, well defined patterns become impossible.

Nanometer Technology Fabrication Trends The relentless drive for density. A smaller IC allows for: –More functionality The next generation IC — the System-on-a-Chip (SoC) –Increased speed Opens new application areas such as communications Allows new capabilities such as mixed-signal IC –Lower power dissipation Heat and managing it is becoming an every increasing cost component in high performance systems –Reduced manufacturing cost compared with board-level integration Larger wafers allow for: Lower per/chip cost

Nanometer Technology IC Design Trends The increasing trend to mixed signal (hybrid) IC –Combining analogue (radio) and digital (computing) circuits Systems on Chip (SoC) v. ASIC –External IP suppliers –Mixed signal (hybrids) –Shorter design times? Validating complex designs –Design-for-Testability (DFT) Build-in Self-Test (BIST) Automated Test Pattern Generation (ATPG)

Nanometer Technology Testing Issues Obstacles –DFT/ATPG scan chains have a significant impact on chip area and performance but no realistic alternatives exists Design for Testability –SoC testing will need more sophisticated ATPG algorithms Fewer design restrictions –Back-end design process is becoming more difficult Less DFT logic

Nanometer Technology Testing Trends Testability –Growing vector sizes and test times continue to be key –On-chip vector decompressors and compressors can improve efficiency Parallel processing –Improves efficiency by allowing new ATPG algorithms to split tasks between processors Configurable scan –Allows splitting a design into a small number of separate blocks –ATPG run for each block from the top level of the design with little loss of efficiency Design for testability: separating the myths from reality

Nanometer Technology Summary Moore’s law shows now signs of slowing –Complexity is driving the need for better tools and methods for IC fabrication, design and test The next generation 90 nm technology will –open new market opportunities –improve performance of existing designs –reduce fabrication costs through reducing chip size New testing technologies will be critical in helping to reduce costs