Indium Phosphide and Related Material Conference 2006 Zach Griffith and Mark J.W. Rodwell Department of Electrical and Computer Engineering University of California, Santa Barbara, CA, , USA Xiao-Ming Fang, Dmitri Loubychev, Ying Wu, Joel M. Fastenau, and Amy Liu IQE Inc. 119 Bethlehem, PA 18015, USA , fax InGaAs / InP DHBTs with a 75nm collector, 20nm base demonstrating 544 GHz f , BV CEO = 3.2V, and BV CBO = 3.4V

High speed HBTs: some standard figures of merit Small signal current gain cut-off frequency (from H 21 )… Power gain cut-off frequency (from U)… Collector capacitance charging time when switching…

Present Status of Fast Transistors

Bipolar Transistor Scaling Laws & Scaling Roadmaps key device parameterrequired change collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.414:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged Scaling Laws: design changes required to double transistor bandwidth Technology Roadmap through 330 GHz digital clock rate key figures of merit for logic speed Key scaling challenges emitter & base contact resistivity current density→ device heating collector-base junction width scaling & Yield !

DC, RF performance—100 nm collector, 30 nm base Summary of device parameters— Average   40, V BR, CEO = 3.1 V Emitter contact (from RF extraction), R cont  7.8  m 2 Base (from TLM) : R sheet = 629  /sq, R cont = 6.2  m 2 Collector (from TLM) : R sheet = 12.9  /sq, R cont = 4.0  m 2 Z. Griffith, IPRM 2005, Glasgow, Scotland

Layer structure nm collector DHBT Thickness (nm)MaterialDoping cm -3 Description 10In 0.85 Ga 0.15 As 5  : Si Emitter cap 15In x Ga 1-x As > 4  : Si Emitter cap grading 10In 0.53 Ga 0.47 As 4  : Si Emitter 70InP 3  : Si Emitter 10InP 1  : Si Emitter 40InP 8  : Si Emitter 20InGaAs 8-6  : C Base 10In 0.53 Ga 0.47 As 3  : Si Setback 24InGaAs / InAlAs 3  : Si B-C Grade 3InP 3  : Si Pulse doping 38InP 3  : Si Collector 5InP 1.5  : Si Sub Collector 7.5In 0.53 Ga 0.47 As 2  : Si Sub Collector 300InP 2  : Si Sub Collector SubstrateSI : InP Objective : Thin collector and base for decreased electron transit time High f  device with moderate f max Investigate J max before current blocking in the base-collector grade What is the HBT breakdown at this collector scaling node?

Average   50, BV CEO = 3.2 V, BV CBO = 3.4 V ( I c = 50  A) Emitter contact (from RF extraction), R cont  8.6  m 2 Base (from TLM) : R sheet = 805  /sq, R cont = 16  m 2 Collector (from TLM) : R sheet = 12.0  /sq, R cont = 4.7  m 2 InP DHBT: 600 nm lithography, 75 nm collector, 20 nm base Peak f  Peak f max DC characteristics RF characteristics A je = 0.65  4.3  m 2, I b,step = 175  A

Experimental Measurement of Temperature Rise …thermal feedback coefficient  = 8.40  V/K at J e = 5.5 mA/  m 2 Temperature rise calculated by measuring I C,  V CB and  V BE 100nm collector,  JA =  V cb (K/mW)  JA = V cb V cb 2 (K/mW)

Small signal equivalent circuit and C cb vs bias Total forward delay (2  f  ) -1 = psec Base and collector transit time = psec Delays associated with C cb account for 77.5 fsec this is ~ 26% of the total delay Increased lateral scaling of the HBT footprint required f  = 544 GHz No evidence of Kirk effect until 8-9 mA/  m 2 at V cb = 0.0V At higher J e and V cb, no C cb increase until J e > 13mA/  m 2 However, f  and f max have decreased at these biases Not clear if intervalley scattering or increased temperature are the cause

High power density operation of 75 nm collector InP HBTs InP SHBT—InGaAs base and collector Type-II DHBT—GaAsSb base, InP collector B.F. Chu-Kung et al., IEE Letters, Vol. 40, No. 20, 2004 W. Hafez et al., IEE Letters, Vol. 39, No. 20, 2003 f  / f max = 358 / 194 GHz f  / f max = 509 / 219 GHz Type-I DHBT—InGaAs base, InP collector, ternary B-C grading f  / f max = 544 / 347 GHz InP SHBTs and InP Type-II DHBTs have yet to demonstrate high power density ( > 12 mW/  m 2 ) operation at moderate voltages InP Type-I DHBTs however can operate within 20% of BV CEO while dissipating ~ 18 mW/  m 2 What is more important for digital logic? – BV CEO, Safe Operating Area (SOA), or both…?

Common emitter and base breakdown of UCSB InP Type-I DHBTs Collector thicknesses, T c 50µA — Breakdown measurements for UCSB InP DHBTs using the same emitter AND collector dimensions — All HBTs utilize the same device formation techniques and Benzocyclobutene (BCB) passivation

What have we been doing at UCSB to scale the HBT? …they include New UCSB Nanofab stepper system—GCA Autostep 200 Updated photoresist processes

How the HBT footprint has been improved (at 0.6 µm) Old device footprint New device footprint Improved alignment, Semiconductor underneath the base post etched twice

0.35 µm emitter junction, W c /W e ~ 2.1 (similar ratio as old process) Note: Emitter metal height ~ 750 nm

0.35 µm emitter junction, W c /W e ~ 1.8 Note: Emitter metal height ~ 750 nm

Conclusion A record 544 GHz f  has been demonstrated for an InP DHBT The trend in C cb with bias is consistent for 75nm across a range of bias The 20nm base having a nominal doping of 7  :C had a hole mobility of ~ 55 cm 2 /V  sec The HBT breakdown voltage for this device is similar to the values demonstrated for InP Type-II DHBTs (collector all InP) Lateral scaling the HBT footprint is needed… – Reduction of C cb for increased f  – Narrow mesa for reduced R bb and more balanced values of f  and f max This work was supported DARPA under the TFAST program, N C-8080