AN ASYNCHRONOUS BUS BRIDGE FOR PARTITIONED MULTI-SOC ARCHITECTURES ON FPGAS REPORTER: HSUAN-JU LI 2014/04/09 Field Programmable Logic and Applications (FPL), rd International Conference on, Sept. (2013) Daniel Kliem, Sven-Ole Voigt

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 2

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 3

Introduction Software applications of safety- and security-critical embedded systems are often divided into several self-contained functions. Between individual system partitions and functions. We use segregation to confine error propagation. Soft processors are one order of magnitude slower in terms of operating frequency than hard-wired devices. 4

Introduction(cont.) Current FPGA families provide wide and fast memory attachments mostly implemented as hard macros that are faster than configurable logic. There is a performance gap between soft processors and the memory attachment. Propose an architecture combines : The specific needs of partitioned software. The flexibility of reconfigurable hardware. 5

Introduction(cont.) Multiple self-contained systems on a single platform FPGA Shares available memory bandwidth among the systems In a predictable and scalable way. The main building blocks of the proposed architecture Secure bus bridges that are used to form a segregated hierarchy of memory busses. 6

Introduction(cont.) With secure bus bridges, it is possible to use soft processors for safety and security-critical functions. To reach high assurance levels with far less effort. 7

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 8

Architecture And Related Work Architecture that achieves domain segregation with Secure Bus Bridges. 9 On-chip (Replicated local resources) Off-chip (Shared for cost reduction.)

Architecture And Related Work(cont.) Multi-Processor SoCs(MPSoCs) often comprise shared caches. CPUs and I/O units that are assigned to one particular software function Influence execution times of other functions on different cores. The Worst-Case Execution Time (WCET) of real-time applications on MPSoCs is less predictable MPSoCs with Multi-Port Memory Controllers (MPMCs) Connecting the local systems to individual ports. Would be scalable in terms of performance. 10

Architecture And Related Work(cont.) Backbone-based approach is modular and uses individually verifiable SECBRGs Keep segregation and memory attachment in different places. 11

Architecture And Related Work(cont.) 12 Local resources exclusively used Neither interrupts nor interface overload propagate into neighboring systems.

Architecture And Related Work(cont.) 13 Necessary spatial segregation by address translation. Non- overlapping memory partitions Caching can be implemented without coherency support between different bridges!!

Architecture And Related Work(cont.) If the backbone bandwidth was larger than the accumulated local bus bandwidths. Multi-system architecture would scale perfectly. The asynchronous SECBRGs can connect the local busses to wider and faster backbones. Memory access temporal conflicts occur at a lower rate. Scalability for multiple local systems is ensured. 14

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 15

Asynchronous Secure Bridge 16

Asynchronous Secure Bridge(cont.) -Command Queue and Result Queue 17 Implemented as FPGA-specific hard macro blocks (BRAMs)

Asynchronous Secure Bridge(cont.) -Address Translation unit 18 Exclusive non-overlapping main memory areas (spatial segregation).

Asynchronous Secure Bridge(cont.) -Bridge Slave and Cache Controller (BSCC) 19 Copy-back caching strategy with valid and dirty flags Cache hit: Local accesses are directly serviced by the BSCC. Cache miss: Fetch commands are placed into the CQ. (Address and size of the data)

Asynchronous Secure Bridge(cont.) -Burst Unit (BU) 20 Expands the fetch commands from CQ to multiple sequential read operations (bursts). Provides them to the Bridge Master Controller (BMC).

Asynchronous Secure Bridge(cont.) -Case of cache cell replacement(to service a cache miss) 21 Fetch and write commands are finally issued out-of-order by the BMC. The BSCC can proceed with the replacement operation of a cache line while the BMC services the previous fetch.

Asynchronous Secure Bridge(cont.) -Case of cache cell replacement(to service a cache miss) Although the BSCC blocks the waiting local master until fetched data arrives in the RQ. It does not wait until all write commands are serviced by the BMC Queue latency does not block the cache with this scheme. 22

Asynchronous Secure Bridge(cont.) To reduce backbone utilization and to achieve scalable performance. Caching, bursting, out-of-order prefetching, and different clock ratios are used. To ensures exclusive access to memory locations. Copy-back caching and out-of-order issuing is possible. Complex cache coherence mechanisms are avoided which leads to simpler and more scalable system designs. 23

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 24

Multi-System FPGA Designs Asynchronous secure bridges Without relaxing the timing constraints Improves place-and-route even when the same frequency is used in all domains. Local busses and the backbone can be driven by independent clocks. 25

Multi-System FPGA Designs(cont.) Prototype implementations on the open source VHDL IP-core library GRLIB by Aeroflex Gaisler. Xilinx ML605 board (Virtex 6 LX240T). One- to eight-fold GRLIB-based prototype designs with clock frequencies as high as 133 MHz. 26

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 27

Benchmarks Results And Discussion The Relative Execution Time (RET) and the Backbone Idle Ratio (BIR) RET: The quotient of the measured local clock ticks spent by a benchmark program divided by a reference tick value. BIR: Relates the idle cycles of the backbone to the total amount of cycles at backbone frequency. 28

Benchmarks Results And Discussion(cont.) T 29

Outline Introduction Architecture And Related Work Asynchronous Secure Bridge Multi-System FPGA Designs Benchmarks Results And Discussion Conclusion 30

Conclusion A novel design of an asynchronous secure bus bridge that partitions multi-SoC FPGA designs into multiple clock domains and reliably shares available bandwidth among multiple soft processor system. Individual clock domains ensure repeatable place-and-route results that scale well with increasing numbers of local systems. The proposed architecture is able to overcome this bandwidth gap and to put soft processors to practical use for safety- and security-critical applications. 31

THANK YOU 32