A Survey on Interlaken Protocol for Network Applications Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. Authors:Gaidhani Dhananjay Shekhar, A.Yogaraj. Publisher:International Journal on Recent and Innovation Trends in Computing and Communication (IJRITCC) 2015 Presenter:Chun-Yu, Li Date:2015/9/30

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 2

Technology Evolution (1/3) Components with gigabit-scale throughput traditionally have data buses running about 100Mbps per pin. Differential signaling technology enables components with throughput on the order of 10Gbps. New serial technology with clock and data recovery enables components with multiple of 100Gbps. Computer & Internet Architecture Lab CSIE NCKU 3

Technology Evolution (2/3). Computer & Internet Architecture Lab CSIE NCKU 4

Technology Evolution (3/3) Interlaken was invented by Cisco Systems. It is an interconnect protocol optimized for high- bandwidth and reliable packet transfer. It works as an interface between 1st and 2nd layer of OSI model. It takes advantages of two dominant high-speed chip- to-chip interface. SPI4.2 XAUI Computer & Internet Architecture Lab CSIE NCKU 5

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 6

SPI4.2 (1/3) SPI4.2 is a protocol used for data transfer between link layer device and physical layer device. It is published by the Optical Internetworking Forum. It aggregate bandwidths of OC192 ATM and packet over SONET ( Synchronous Optical Networking ), as well as for 10 Gb/s Ethernet applications. Computer & Internet Architecture Lab CSIE NCKU 7

SPI4.2 (2/3) On both the transmit and receive interfaces, FIFO status is sent separately from the corresponding data path. Computer & Internet Architecture Lab CSIE NCKU 8

SPI4.2 (3/3) Point-to-Point connection (i.e. between single PHY & single Link Layer device), Support for 256 ports, Transmit & Receive data path is 16 bit, Channelization, programmable burst size & per- channel back pressure. Computer & Internet Architecture Lab CSIE NCKU 9

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 10

XAUI (1/3) It is developed by IEEE 802.3ae 10 Gigabit Ethernet Task Force. XAUI is a standard for extending the XGMII between the MAC and PHY layer of 10 Gigabit Ethernet. XGMII (10 Gigabit Media Independent Interface) Provides a 10 Gb/s differential signal pipeline. The separate transmission of clock and data coupled. Its timing requirement to latch data on both the rising and falling edges of the clock. Which result in significant challenge in routing the bus more than the recommended short distance of 7 cm. Computer & Internet Architecture Lab CSIE NCKU 11

XAUI (2/3) Computer & Internet Architecture Lab CSIE NCKU 12 XGXS: XGMII Extender Sublayer

XAUI (3/3) Computer & Internet Architecture Lab CSIE NCKU 13 It is a narrow 4-lane interface, offers long reach, Independent transmit and receive data paths, Differential signaling with low voltage swing, Utilization of 8b/10b encoding, It suits a variety of implementations like FR4 on PCB, backplanes & cables, As a packet-based interface it lacks channelization & flow control.

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 14

Design Goals (1/13) Computer & Internet Architecture Lab CSIE NCKU 15 Bandwidth Range Interlaken should not have specific upper limit. It is primarily targeted for 10Gbps to 100Gbps. Scalability The following two parameters determine the connection bandwidth: Number of serial lanes in the interface, Frequency of each lane.

Design Goals (2/13) Computer & Internet Architecture Lab CSIE NCKU 16 Number of serial lanes in the interface The effective bandwidth of Interlaken protocol corresponds to the number of lanes on which it is working.

Design Goals (3/13) Computer & Internet Architecture Lab CSIE NCKU 17 Frequency of each lane Effective bandwidth also scales directly with the per-lane bit rate. For example, a Gbps port can carry half the payload of a 6.25 Gbps.

Design Goals (4/13) Computer & Internet Architecture Lab CSIE NCKU 18 Since bandwidth can be increased by either adding more lanes or by increasing the bit rate per lane, Interlaken is a very scalable interface.

Design Goals (5/13) Computer & Internet Architecture Lab CSIE NCKU 19 Flexibility ICs with different capacities in a single physical interface can be split up into multiple lower-speed physical interfaces.

Design Goals (6/13) Computer & Internet Architecture Lab CSIE NCKU 20 Channelization To support varying number of channels Interlaken should have support to operate on different number of channels available for the particular application. There are two basic methods of sending packets across an interface: Non-interleaved Transfers, Interleaved Transfers.

Design Goals (7/13) Computer & Internet Architecture Lab CSIE NCKU 21 Non-interleaved Transfers The transfer of a packet is always completed before transfers are started on another channel.

Design Goals (8/13) Computer & Internet Architecture Lab CSIE NCKU 22 Interleaved Transfers Each channel transmits only a small fragment (burst) of a packet before moving to the next channel.

Design Goals (9/13) Computer & Internet Architecture Lab CSIE NCKU 23 Burst control word with channel field. Applications that support to 64 K channels by using the dual-use field combined with the normal 8-bit channel field.

Design Goals (10/13) Computer & Internet Architecture Lab CSIE NCKU 24 Resiliency Use of strong cyclic redundancy check (CRC) and technology known as scrambling. The health of each serial link is continuously and transparently monitored.

Design Goals (11/13) Computer & Internet Architecture Lab CSIE NCKU 25 Burst CRC24 Coverage

Design Goals (12/13) Computer & Internet Architecture Lab CSIE NCKU 26 SerDes (Serializer/Deserializer) lanes would make it difficult to ensure that errored packets could be adequately detected.

Design Goals (13/13) Computer & Internet Architecture Lab CSIE NCKU 27 Scrambling Since Interlaken uses a scrambler, there must be a methodology to synchronize the receiver to the scrambler-state. The receiver uses the recovered scrambler-state to synchronize its scrambler and then de-scramble the data stream. E.g. Linear Feedback Shift Register (LFSR)

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 28

Highlights of Interlaken Protocol (1/1) Support for 256 communications channels, or up to 64K with channel extension. A simple control word structure to delineate packets, similar in function to SPI4.2. Protocol independence from the number of SerDes lanes and SerDes rates. 64B/67B data encoding and scrambling. Performance that scales with the number of lanes. Computer & Internet Architecture Lab CSIE NCKU 29

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 30

Implementation History (1/1) Computer & Internet Architecture Lab CSIE NCKU 31

Outline Introduction Technology Evolution SPI4.2 XAUI Interlaken Protocol Design Goals Highlights of Interlaken Protocol Existing Work Implementation History Summary of Various IPs Computer & Internet Architecture Lab CSIE NCKU 32

Summary of Various IPs (1/1) Computer & Internet Architecture Lab CSIE NCKU 33